Patent US3859644A successfully refreshed from Google Patents.
US3859644A
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Temperature responsive cooking timer
Assignee: Burger Chef Systems Inc
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Filing: 1973-04-24
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Granted: 1975-01-07
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Expires: 1993-04-24
Abstract
Abstract A digital cooking timer responsive to the temperature of a cooking medium and incorporating minimum and maximum time decoders to insure that the cooking period is within a predetermined range is described. An interval timer sets up a counting period upon immersion of the product in the cooking medium but is inhibited from starting its counting function by the minimum time decoder until elapse of a fixed time period. After elapse of the fixed time period, the interval timer is enabled when and if the cooking medium reaches a predetermined temperature. The maximum time decoder provides an override control that energizes the control device after a fixed period in the absence of an energizing signal for the control device from the interval timer.
Inventors
- 👤 Duane C Main
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:44
CPC Classifications
G; G05; G05D; G05D23/00; G05D23/19; G05D23/1951
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
173 words
A temperature responsive cooking timer for controlling the cooking time of a cooker comprising: means for sensing the cooking temperature of the cooker and providing an output signal which is a function of the temperature of the cooking medium; a comparator responsive to said output signal for developing a control signal when the temperature of the cooking medium reaches a predetermined value, pulse generator means for producing a continuous train of pulses equally spaced at a predetermined interval; a pulse counter for totalling the individual pulses generated by said pulse generator; a maximum time counter responsive to a predetermined count of said pulse counter; a minimum time counter responsive to a predetermined count of said pulse counter for providing an inhibit signal corresponding to a predetermined count; an interval pulse counter responsive to said control signal and said inhibit signal for totalling the individual pulses generated by said pulse generator, and a control means responsive to an output of said maximum time counter or said interval pulse counter corresponding to a predetermined count.
Claim 2
Dependent Claim
173 words
A temperature responsive cooking timer for controlling the cooking time of a cooker comprising: means for sensing the cooking temperature of the cooker and providing an output signal which is a function of the temperature of the cooking medium; a comparator responsive to said output signal for developing a control signal when the temperature of the cooking medium reaches a predetermined value, pulse generator means for producing a continuous train of pulses equally spaced at a predetermined interval; a pulse counter for totalling the individual pulses generated by said pulse generator; a maximum time counter responsive to a predetermined count of said pulse counter; a minimum time counter responsive to a predetermined count of said pulse counter for providing an inhibit signal corresponding to a predetermined count; an interval pulse counter responsive to said control signal and said inhibit signal for totalling the individual pulses generated by said pulse generator, and a control means responsive to an output of said maximum time counter or said interval pulse counter corresponding to a predetermined count.
Claim 3
Dependent Claim
60 words
A timer as defined in claim 1 wherein, said comparator includes: a first voltage divider network for providing a reference voltage potential; a second voltage divider network including a temperature responsive transducer for providing a monitor voltage potential; and means for comparing said reference voltage potential and said monitor voltage potential and for providing an output signal in response thereto.
Claim 4
Dependent Claim
68 words
The apparatus defined in claim 2 wherein, said second voltage divider network includes: a first switch means; a plurality of resistive elements selectively connectable in series with said transducer and said comparing means by said first switch means; a second resistive network selectively connectable to said comparing means by said first switch means; and a second switch means for altering the resistance value of said second resistive network.
Claim 5
Dependent Claim
106 words
A timer as defined in claim 1 further including means for producing a half wave signal, said pulse generator including: a square wave generator responsive to said half wave signal and adapted to provide pulses at a repetition rate equal to the frequency of said half wave signal; a plurality of flip-flops connected in series and sEquentially responsive to the output of said square wave generator; said plurality of flip-flops being adapted to provide a single output pulse in response to 60 output pulses of said square wave generator; and means to reset said plurality of flip-flops in response to initial energization of said power supply.
Claim 6
Dependent Claim
79 words
A timer as defined in claim 1, wherein said pulse counter includes: a plurality of flip-flops connected in series and sequentially responsive to the output of said pulse generator, and adapted to provide first, second; third, fourth, and fifth independent outputs, said independent outputs being adapted to have a sequential progressive relationship to said pulse generator output pulses; and a plurality of logic gates responsive to initial power application to said power supply for resetting said plurality of flip-flops.
Claim 7
Dependent Claim
28 words
A timer as defined in claim 5 wherein, said maximum time counter includes: a two-input NAND gate responsive to said fourth and fifth outputs of said pulse counter.
Claim 8
Dependent Claim
71 words
A timer as defined in claim 5 wherein, said minimum time counter includes: a three-signal NAND gate responsive to said first, second, and third outputs of said pulse counter, a first two-input NAND gate responsive to the output of said three-input NAND gate; and a second two-input NAND gate responsive to the output of said first two-input NAND gate for providing a self holding signal to said first two-input NAND gate.
Claim 9
Dependent Claim
134 words
A timer as defined in claim 1 wherein, said interval pulse counter includes: a first three-input NAND gate responsive to the control signal output of said comparator and inhibit signal output from said minimum time counter; a first flip-flop responsive to the output of said first three input NAND gate, said first flip-flop including a feedback loop to the third input of said first three-input NAND gate; a plurality of series connected flip-flops sequentially responsive to the output of said first flip-flop for providing independent first, second, and third sequentially progressive outputs; a second three-input NAND gate responsive to said first, second, and third sequentially progressive outputs for providing a signal to said alarm means; and a two-input NAND gate responsive to initial energization of said power supply for resetting said plurality of flip-flops.
Claim 10
Dependent Claim
80 words
A timer as defined in claim 1 wherein, said control means includes: a two-input NAND gate connected to receive the output of said interval pulse counter and the output of said maximum time counter; a flip-flop responsive to the output of said two-gate and adapted to be switched between a first and a second state, a normally de-energized relay connected to said flip-flop and adopted to be energized when said flip-flop is switched from said first to said second state.
Claim 11
Dependent Claim
78 words
A timer as defined in claim 1, wherein said comparing means includes: a differential amplifier and further including a transistor including a bias network for holding said transistor normally nonconducting; means for connecting said transistor to the output of said differential amplifier for rendering said transistor conductive in response to an output thereof; and means responsive to the state of said transistor for providing an indication corresponding to the presence of an output signal from said differential amplifier.
References Cited (Backward Citations)
US3290486A
Cited
US3413446A
Cited
US3688295A
Cited
US3611336A
Cited
US3632986A
Cited
US3745308A
Cited
US3751632A
Cited
US3778798A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-06 | 1978-07-08 | 1979-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-06 | 1982-07-08 | 1983-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-06 | 1986-07-08 | 1987-01-07 | $7700.00 | Window Closed / Lapsed |