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US3859640A
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Concurrent data address and refresh control for a volatile lsi memory system
Assignee: Samsung Electronics Co Ltd
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Filing: 1973-10-01
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Granted: 1975-01-07
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Expires: 1993-10-01
Abstract
Abstract A novel internal organization of an LSI memory chip for optimum refresh control is disclosed. The chip is organized in a plurality of N similar memory loops in which the M data bits that are stored in each memory loop are serially shifted therethrough in an end-around fashion for the data reading, writing and refreshing operations. The novel internal organization includes partitioning the N memory loops into S subgroups of 2n memory loops per subgroup, N S2n, where n is a positive integer of 0 or greater and then refreshing the 2n memory loops of each of the S subgroups at a refresh clock signal frequency FR that is a submultiple of the fundamental data clock signal frequency FD, FD SFR, at which the normal data read/write operations are performed. A fundamental data clock signal source of frequency FD drives a refresh clock signal source that sequentially and continuously refreshes each of the N memory loops at the refresh clock frequency FR using the internal selection gates of the LSI memory chip rather than using the internal memory loop address decoder; this permits the refresh operation to be an entirely internal operation independent of external memory control.
Inventors
- 👤 Delvin D Eberlein
- 👤 Robert M Englund
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:20
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/188; G11C19/28; G11C19/287
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
303 words
The method of organizing a volatile LSI memory system for refresh control in which the memory system is organized in a plurality of N separate but similar serial-end-around-shiftregister-forming memory loops each of which N memory loops is addressed by an associated separate one of N selection gates, the method comprising: generating a data clock signal comprising a continuous series of data clock signal pulses of a data clock signal frequency FD; generating a sequential refresh clock signal comprising a continuously recurring series of N sequential refresh clock signal pulses at said data clock signal frequency FD, each one of said N sequential refresh clock signal pulses recurring at a refresh clock signal frequency FR FD/N; generating a data address select signal; coupling said data clock signal pulses in parallel to the N selection gates of said N memory loops; sequentially coupling each separate one of said N sequential refresh clock signal pulses to the associated one of said N selection gates for gating the concurrent one of said data clock signal pulses through to the associated memory loop for sequentially refreshing said N memory loops at said refresh clock signal frequency FR; coupling said data address select signal to only a selected one of said N selection gates of said N memory loops for gating said data clock signal pulses to the associated selected one of said N memory loops and shifting the data bits in said associated selected one of said N memory loops in an end-around manner at said data clock signal frequency FD; said data address select signal and one of said sequential refresh clock signal pulses concurrently occurring at said selected one of said N selection gates of said N memory loops for concurrently gating said data clock signal to said associated selected one of said N memory loops.
Claim 2
Independent Claim
303 words
The method of organizing a volatile LSI memory system for refresh control in which the memory system is organized in a plurality of N separate but similar serial-end-around-shiftregister-forming memory loops each of which N memory loops is addressed by an associated separate one of N selection gates, the method comprising: generating a data clock signal comprising a continuous series of data clock signal pulses of a data clock signal frequency FD; generating a sequential refresh clock signal comprising a continuously recurring series of N sequential refresh clock signal pulses at said data clock signal frequency FD, each one of said N sequential refresh clock signal pulses recurring at a refresh clock signal frequency FR FD/N; generating a data address select signal; coupling said data clock signal pulses in parallel to the N selection gates of said N memory loops; sequentially coupling each separate one of said N sequential refresh clock signal pulses to the associated one of said N selection gates for gating the concurrent one of said data clock signal pulses through to the associated memory loop for sequentially refreshing said N memory loops at said refresh clock signal frequency FR; coupling said data address select signal to only a selected one of said N selection gates of said N memory loops for gating said data clock signal pulses to the associated selected one of said N memory loops and shifting the data bits in said associated selected one of said N memory loops in an end-around manner at said data clock signal frequency FD; said data address select signal and one of said sequential refresh clock signal pulses concurrently occurring at said selected one of said N selection gates of said N memory loops for concurrently gating said data clock signal to said associated selected one of said N memory loops.
Claim 3
Independent Claim
332 words
The method of organizing a volatile LSI memory system for refresh control in which the memory system is organized in a plurality of N separate but similar serial-end-around-shift-register-forming memory loops each of which N memory loops is addressed by an associated separate one of N selection gates, the method comprising: partitioning said N memory loops into S subgroups of 2n memory loops per subgroup, where N S2n; generating a data clock signal comprising a continuous series of data clock signal pulses of a data clock signal frequency FD; generating a sequential refresh clock signal comprising a continuously recurring series of S sequential refresh clock signal pulses at said data clock signal frequency FD, each one of said S sequential refresh clock signal pulses recurring at a refresh clock signal frequency FR FD/s; generating a data address select signal; coupling said data clock signal in parallel to the N selection gates of said N memory loops; sequentially coupling each separate one of said S sequential refresh clock signal pulses in parallel to the 2n selection gates of a corresponding one of said S subgroups for gating the concurrent ones of said data clock signal pulses in parallel through to the associated 2n memory loops of each subgroup and sequentially refreshing each subgroup of 2n memory loops at said refresh clock signal frequency FR; coupling said data address select signal to only a selected one of said N selection gates of said N memory loops for gating said data clock signal to the associated selected one of said N memory loops and shifting the data bits in said associateD selected one of said N memory loops in an end-around manner at said data clock signal frequency FD; said data address select signal and one of said sequential refresh clock signal pulses concurrently occurring at said selected one of said N selection gates of said N memory loops for concurrently gating said data clock signal to said associated selected one of said N memory loops.
Claim 4
Independent Claim
332 words
The method of organizing a volatile LSI memory system for refresh control in which the memory system is organized in a plurality of N separate but similar serial-end-around-shift-register-forming memory loops each of which N memory loops is addressed by an associated separate one of N selection gates, the method comprising: partitioning said N memory loops into S subgroups of 2n memory loops per subgroup, where N S2n; generating a data clock signal comprising a continuous series of data clock signal pulses of a data clock signal frequency FD; generating a sequential refresh clock signal comprising a continuously recurring series of S sequential refresh clock signal pulses at said data clock signal frequency FD, each one of said S sequential refresh clock signal pulses recurring at a refresh clock signal frequency FR FD/s; generating a data address select signal; coupling said data clock signal in parallel to the N selection gates of said N memory loops; sequentially coupling each separate one of said S sequential refresh clock signal pulses in parallel to the 2n selection gates of a corresponding one of said S subgroups for gating the concurrent ones of said data clock signal pulses in parallel through to the associated 2n memory loops of each subgroup and sequentially refreshing each subgroup of 2n memory loops at said refresh clock signal frequency FR; coupling said data address select signal to only a selected one of said N selection gates of said N memory loops for gating said data clock signal to the associated selected one of said N memory loops and shifting the data bits in said associateD selected one of said N memory loops in an end-around manner at said data clock signal frequency FD; said data address select signal and one of said sequential refresh clock signal pulses concurrently occurring at said selected one of said N selection gates of said N memory loops for concurrently gating said data clock signal to said associated selected one of said N memory loops.
Claim 5
Dependent Claim
321 words
A volatile LSI memory system, comprising: N memory loops, each of said N memory loops including an associated separate selection gating means; data clock signal generator means for generating a data clock signal comprising a continuous series of data clock signal pulses of a data clock signal frequency FD; means for concurrently coupling said data clock signal to the selection gating means of all of said N memory loops; refresh clock signal generator means, driven by said data clock signal generator means, for generating a sequential refresh clock signal comprising a continuously recurring series of N refresh clock signal pulses at said data clock signal frequency FD, each separate one of said N refresh clock signal pulses recurring at the refresh clock signal frequency FR FD/N; means for coupling each separate one of said N refresh clock signal pulses to the selection gating means of only the associated one of said N memory loops for continuously refreshing each of said N memory loops at said refresh clock signal frequency FR; N separate address lines, each of said address lines coupled only to the selection gating means of the associated one of said N memory loops; address decoder means decoding a multibit address word and coupling a data address select signal to only a selected one of said N address lines for reading the information stored in at least a part of the associated selected one of said N memory loops; said refresh clock signal generator means continuously and sequentially refreshing each of said N memory loops at said refresh clock signal frequency FR while concurrently said address decoder means is addressing said N memory loops at said data clock signal frequency FD, said refresh clock signal and said data address select signal concurrently being coupled to the selection gating means of said selected one of said N address lines for concurrently effecting said associated selected one of said N memory loops.
Claim 6
Dependent Claim
321 words
A volatile LSI memory system, comprising: N memory loops, each of said N memory loops including an associated separate selection gating means; data clock signal generator means for generating a data clock signal comprising a continuous series of data clock signal pulses of a data clock signal frequency FD; means for concurrently coupling said data clock signal to the selection gating means of all of said N memory loops; refresh clock signal generator means, driven by said data clock signal generator means, for generating a sequential refresh clock signal comprising a continuously recurring series of N refresh clock signal pulses at said data clock signal frequency FD, each separate one of said N refresh clock signal pulses recurring at the refresh clock signal frequency FR FD/N; means for coupling each separate one of said N refresh clock signal pulses to the selection gating means of only the associated one of said N memory loops for continuously refreshing each of said N memory loops at said refresh clock signal frequency FR; N separate address lines, each of said address lines coupled only to the selection gating means of the associated one of said N memory loops; address decoder means decoding a multibit address word and coupling a data address select signal to only a selected one of said N address lines for reading the information stored in at least a part of the associated selected one of said N memory loops; said refresh clock signal generator means continuously and sequentially refreshing each of said N memory loops at said refresh clock signal frequency FR while concurrently said address decoder means is addressing said N memory loops at said data clock signal frequency FD, said refresh clock signal and said data address select signal concurrently being coupled to the selection gating means of said selected one of said N address lines for concurrently effecting said associated selected one of said N memory loops.
Claim 7
Dependent Claim
269 words
A volatile LSI memory system, comprising: N memory loops each of which memory loops includes and is addressed by an associated selection gating means; an address decoder decoding a multibit address word and coupling a data address select signal to a selected one of said selection gating means for reading the information from at least a part of the associated selected one of said N memory loops; means for coupling a data clock signal comprising a continuous series of data clock signal pulses of a data clock signal frequency FD in parallel to all of said selection gating means; means driven by said data clock signal for generating a sequential refresh clock signal comprising a continuously recurring series of S sequential refresh clock signal pulses at said data clock signal frequency FD, each separate one of said S sequential refresh clock signal pulses recurring at a sequential refresh clock signal frequency FR FD/S; means separately coupling an associated separate one of said S sequential refresh clock signal pulses in parallel to the 2n selection gating means of an associated one of S subgroups of said memory loops partitioning said N memory loops into S subgroups of 2n memory loops per subgroup, where N S2n, for concurrently refreshing in parallel the 2n memory loops of each of the S subgroups and continuously sequentially refreshing the S subgroups of the LSI Memory; said refresh clock signal and said data address select signal concurrently being coupled to the selection gating means of said selected one of said N address lines for concurrently effecting said associated selected one of said N memory loops.
Claim 8
Dependent Claim
269 words
A volatile LSI memory system, comprising: N memory loops each of which memory loops includes and is addressed by an associated selection gating means; an address decoder decoding a multibit address word and coupling a data address select signal to a selected one of said selection gating means for reading the information from at least a part of the associated selected one of said N memory loops; means for coupling a data clock signal comprising a continuous series of data clock signal pulses of a data clock signal frequency FD in parallel to all of said selection gating means; means driven by said data clock signal for generating a sequential refresh clock signal comprising a continuously recurring series of S sequential refresh clock signal pulses at said data clock signal frequency FD, each separate one of said S sequential refresh clock signal pulses recurring at a sequential refresh clock signal frequency FR FD/S; means separately coupling an associated separate one of said S sequential refresh clock signal pulses in parallel to the 2n selection gating means of an associated one of S subgroups of said memory loops partitioning said N memory loops into S subgroups of 2n memory loops per subgroup, where N S2n, for concurrently refreshing in parallel the 2n memory loops of each of the S subgroups and continuously sequentially refreshing the S subgroups of the LSI Memory; said refresh clock signal and said data address select signal concurrently being coupled to the selection gating means of said selected one of said N address lines for concurrently effecting said associated selected one of said N memory loops.
Claim 9
Dependent Claim
341 words
a volatile LSI memory system, comprising: N separate but similar serial-end-around-shift-register-forming memory loops, each of said N memory loops including as associated separate pair of 01 and 02 selection gates; data clock signal generator means for generating a two-phase data clock signal 01 and 02 comprising a continuous series of alternate data clock signal 01 and 02 pulses, each series of a data clock signal frequency FD; means for coupling said data signal 01 and 02 in parallel to the 01 and 02 selection gates, respectively, of each of said N memory loops; refresh clock signal generator means, driven by said data clock signal generator means, for generating a sequential refresh clock signal comprising a continuously recurring series of S sequential refresh clock signal pulses at said data clock signal frequency FD, each of said S sequential refresh clock signal pulses recurring at the sequential refresh clock signal frequency FR FD/S; S separate refresh clock signal lines, each separate one coupled in parallel to 2n pair of 01 and 02 selection gates for partitioning said N memory loops into S subgroups of 2n memory loops per subgroup, where N S2n; means coupling each separate one of said S sequential refresh clock signal pulses to an associated one of said S refresh clock signal lines for concurrently refreshing the 2n memory loops of each subgroup at said sequential refresh clock signal frequency FR and continuously sequentially refreshing the S subgroups at said data clock signal frequency FD; separate address lines, each of said N address lines coupled only to the pair of 01 and 02 selection gates of the associated one of said N memory loops; address decoder means for decoding a multibit address word and coupling a data address select signal to only a selected one of said N address lines; said refresh clock signal generator means refreshing the 2n memory loops of one of said subgroups while concurrently said address decoder means is reading out of one of the 2n memory loops of the one subgroup that is being refreshed.
Claim 10
Dependent Claim
341 words
a volatile LSI memory system, comprising: N separate but similar serial-end-around-shift-register-forming memory loops, each of said N memory loops including as associated separate pair of 01 and 02 selection gates; data clock signal generator means for generating a two-phase data clock signal 01 and 02 comprising a continuous series of alternate data clock signal 01 and 02 pulses, each series of a data clock signal frequency FD; means for coupling said data signal 01 and 02 in parallel to the 01 and 02 selection gates, respectively, of each of said N memory loops; refresh clock signal generator means, driven by said data clock signal generator means, for generating a sequential refresh clock signal comprising a continuously recurring series of S sequential refresh clock signal pulses at said data clock signal frequency FD, each of said S sequential refresh clock signal pulses recurring at the sequential refresh clock signal frequency FR FD/S; S separate refresh clock signal lines, each separate one coupled in parallel to 2n pair of 01 and 02 selection gates for partitioning said N memory loops into S subgroups of 2n memory loops per subgroup, where N S2n; means coupling each separate one of said S sequential refresh clock signal pulses to an associated one of said S refresh clock signal lines for concurrently refreshing the 2n memory loops of each subgroup at said sequential refresh clock signal frequency FR and continuously sequentially refreshing the S subgroups at said data clock signal frequency FD; separate address lines, each of said N address lines coupled only to the pair of 01 and 02 selection gates of the associated one of said N memory loops; address decoder means for decoding a multibit address word and coupling a data address select signal to only a selected one of said N address lines; said refresh clock signal generator means refreshing the 2n memory loops of one of said subgroups while concurrently said address decoder means is reading out of one of the 2n memory loops of the one subgroup that is being refreshed.
References Cited (Backward Citations)
US3691534A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-06 | 1978-07-08 | 1979-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-06 | 1982-07-08 | 1983-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-06 | 1986-07-08 | 1987-01-07 | $7700.00 | Window Closed / Lapsed |