Device for controlling display output by micro-program

Claim 1

A display control device for a numeric display unit comprising: a shift register (15) having input and output terminals for storing a binary coded numeric information from the input terminals; the numeric display unit (13) having a plurality of digit segments and a plurality of numeric segments in each of said digit segments for displaying the information stored in said shift register; a digit segment drive circuit (13AD) connected to said digit segments of said numeric display unit for selectively energizing said digit segments, said digit segment drive circuit including a first decoder for decoding a plurality of binary codes entered and for selecting one of said digit segments; a numeric segment drive circuit (13KD) for selectively energizing said plurality of numeric segments associated with each of said digit segments, said numeric segment drive circuit including a second decoder for decoding a plurality of binary codes entered and for selecting some or all of said numeric segments; a digit information buffer circuit (121) having output terminals connected to the input terminals of said digit segment drive circuit; a first group of AND gates (121) having output terminals connected to the input terminals of said digit information buffer circuit and each having two input terminals; a numeric information buffer circuit (144) having output terminals connected to the input terminals of said numeric segment drive circuit; a second group of AND gates (143) having output terminals connected to the input terminals of said numeric information buffer circuit and each having two input terminals; an arithmetic unit (18) having output terminals for executing an arithmetic operation and for delivering the operational result to said shift register; a read-only memory (11) composed of a semi-conductor large scale integration circuit having at least a data portion including digit position information stored and a control portion including gate control signal stored therein; means for controlling said first group of AND gates to deliver a digit position information signal to said digit information buffer circuit in response to an application of the digit position information from said data position of said read-only memory to one set of said input terminals thereof as well as an application of the gate control signal from said control portion of said read-only memory to the other set of said input terminals thereof; means for controlling said second group of AND gates to deliver a binary numeric information signal to said numeric information buffer circuit in response to an application of one digit numeric information from said shift register to one set of input terminals thereof as well as an application of the gate control signal from said control portion of said read-only memory to the other set of input terminals thereof; means for controlling said numeric display unit so that said plurality of digit segments are sequentially energized in accordance with the sequence of the digit information stored in said read-only memory and said numeric segments are selectively energized to display the numeric information stored in said shift register in accordance with the gate control signal included in said read-only memory, thereby to display plural digits of numerics on a time division basis.