US3854010A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Time division multiplexing transmission system
Assignee: Hitachi Ltd
•
Filing: 1973-05-18
•
Granted: 1974-12-10
•
Expires: 1993-05-18
Abstract
Abstract A time division multiplexing transmission system transmits first and second information signals in turns at a time rate of an integer ratio, said first and second information signals being divided at periods of first and second signals. At a transmitter end there are provided means for producing said first and second signals and means for forming a digital synchronizing signal having a given relation to said first and second signals, said digital synchronizing signal being composed of a synchronizing information consisting of a pulse chain having a given repetition frequency and a control signal also consisting of a pulse chain. At a receiver end at first said synchronizing information is extracted from an incoming signal and then said control signal is extracted on the basis of said extracted synchronizing information so as to produce first and second synchronizing signals having frequencies which are equal to those of said first and second signals, respectively and said first and second information signals are reproduced by means of said first and second synchronizing signals.
Inventors
- 👤 H Nabeyama
- 👤 T Yoshino
- 👤 T Takezawa
- 👤 A Yanagimachi
- 👤 K Mohri
- 👤 M Eukuda
- 👤 H Yamane
- 👤 E Sawabe
- 👤 T Kayano
- 👤 M Masuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:50
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/20; H04N21/23; H04N21/236; H04J; H04J3/00; H04J3/16; H04J3/1605; H04N1/00; H04N1/00095; H04N1/00098; H04N21/40; H04N21/43; H04N21/434; H04N7/00; H04N7/24; H04N7/52; H04N7/54; H04N7/56
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
548 words
A time division multiplexing transmission system for transmitting first and second information signals in turns at a time rate of a given integer ratio, said first and second information signals being divided at periods of first and second signals, respectively, said transmission system comprises at a transmitter end a signal generator for producing an original signal having a given frequency; a first circuit for producing said first signal having a first frequency which is equal to a fraction of an integer of said given frequency of said original signal; a second circuit for producing said second signal having a second frequency which has a relation of an integer ratio with respect to said first frequency; a third circuit for producing a third signal having a third frequency which is equal to fractions of integers of said first and second frequencies; a fourth circuit for producing a fourth signal having a fourth frequency which is equal to a fraction of an integer of said third frequency; a gate circuit for alternately passing said first and second signals at a time rate of said given integer ratio under a control of a gate signal formed by said fourth signal; and a digital synchronizing signal generator which is triggered by an output signal from said gate circuit and produces a digital synchronizing signal composed of a synchronizing information consisting of a pulse chain of a given repetition frequency and first and second control signals each consisting of a pulse chain, pulses of which pulse chain appear at given time slots in synchronism with occurrence instances of said first, second and third signals, said synchronizing information of the given repetition frequency being of the common waveform in both of said first and second signal periods, but said first control signal which is produced in said first signal period being different from said second control signal which is produced in said second signal period; whereby said synchronizing information and first control signal are inserted in said first information signal divided at said first signal period and said synchronizing information and second control signal are inserted in said second information signal divided at said second signal period, and said transmission system further comprises at a receiver end means for extracting said pulse chain having the given repetition frequency from said synchronizing information of the common waveform inserted in said first and second information signals which have been transmitted in turns at a time rate of said given integer ratio and producing clock pulses having a repetition frequency which is equal to said repetition frequency of said extracted pulse chain; means for extracting said first and second control signals on the basis of the produced clock pulses; and means for forming first and second synchronizing signals having said first and second frequencies, respectively, from said clock pulses, whereby said first and second synchronizing signals and said extracted first and second control signals are collated to each other and said means for forming said first and second synchronizing signals is controlled by a collation output so as to produce said first and second synchronizing signals of said first and second frequencies, respectively, in synchronism with a transmitted signal and said first and second information signals are reproduced by means of said first and second synchronizing signals.
Claim 2
Dependent Claim
548 words
A time division multiplexing transmission system for transmitting first and second information signals in turns at a time rate of a given integer ratio, said first and second information signals being divided at periods of first and second signals, respectively, said transmission system comprises at a transmitter end a signal generator for producing an original signal having a given frequency; a first circuit for producing said first signal having a first frequency which is equal to a fraction of an integer of said given frequency of said original signal; a second circuit for producing said second signal having a second frequency which has a relation of an integer ratio with respect to said first frequency; a third circuit for producing a third signal having a third frequency which is equal to fractions of integers of said first and second frequencies; a fourth circuit for producing a fourth signal having a fourth frequency which is equal to a fraction of an integer of said third frequency; a gate circuit for alternately passing said first and second signals at a time rate of said given integer ratio under a control of a gate signal formed by said fourth signal; and a digital synchronizing signal generator which is triggered by an output signal from said gate circuit and produces a digital synchronizing signal composed of a synchronizing information consisting of a pulse chain of a given repetition frequency and first and second control signals each consisting of a pulse chain, pulses of which pulse chain appear at given time slots in synchronism with occurrence instances of said first, second and third signals, said synchronizing information of the given repetition frequency being of the common waveform in both of said first and second signal periods, but said first control signal which is produced in said first signal period being different from said second control signal which is produced in said second signal period; whereby said synchronizing information and first control signal are inserted in said first information signal divided at said first signal period and said synchronizing information and second control signal are inserted in said second information signal divided at said second signal period, and said transmission system further comprises at a receiver end means for extracting said pulse chain having the given repetition frequency from said synchronizing information of the common waveform inserted in said first and second information signals which have been transmitted in turns at a time rate of said given integer ratio and producing clock pulses having a repetition frequency which is equal to said repetition frequency of said extracted pulse chain; means for extracting said first and second control signals on the basis of the produced clock pulses; and means for forming first and second synchronizing signals having said first and second frequencies, respectively, from said clock pulses, whereby said first and second synchronizing signals and said extracted first and second control signals are collated to each other and said means for forming said first and second synchronizing signals is controlled by a collation output so as to produce said first and second synchronizing signals of said first and second frequencies, respectively, in synchronism with a transmitted signal and said first and second information signals are reproduced by means of said first and second synchronizing signals.
Claim 3
Dependent Claim
41 words
A time division multiplexing transmission system as claimed in claim 1, wherein a period of said pulse chain of said given repetition frequency constructing said synchronizing information is made equal to a period of said original signal of said given frequency.
Claim 4
Dependent Claim
48 words
A time division multiplexing transmission system as claimed in claim 2, wherein at least one of said first and second information signal is a pulse modulation signal and a bit synchronizing signal for decoding said pulse modulation signal is extracted from said pulse chain constracting said synchronizing information.
Claim 5
Dependent Claim
70 words
A time division multiplexing transmission system as claimed in claim 1, wherein said given frequency of said original signal is fp, said first frequency is fa and said second frequency is fb, and these frequencies satisfy the following relation, fp Ifa Jfb here I and J are positive integers and equal to the numbers of waves of the given frequency component in periods of said first and second signals, respectively.
Claim 6
Dependent Claim
73 words
A time division multiplexing transmission system as claimed in claim 1, wherein said first information signal is an audio PCM signal and said second information signal is a video signal of a still picture, and further said first signal is a PCM frame synchronizing signal, said second signal is a video horizontal synchronizing signal and said original signal of the given frequency is a bit synchronizing signal for decoding said audio PCM signal.
Claim 7
Dependent Claim
55 words
A time division multiplexing transmission system as claimed in claim 1, wherein said first information signal is an audio PPM signal and said second information signal is a video signal of a still picture, and further said first signal is a PPM frame synchronizing signal and said second signal is a video horizontal synchronizing signal.
Claim 8
Dependent Claim
55 words
A time division multiplexing transmission system as claimed in claim 1, wherein said first information signal is an audio PAM signal and said second information signal is a video signal of a still picture and further said first signal is a PAM frame synchronizing signal and said second signal is a video horizontal synchronizing signal.
Claim 9
Dependent Claim
54 words
A time division multiplexing transmission system as claimed claim 1, wherein said first information signal is an audio PWM signal and said second information signal is a video signal of a still picture, and further said first signal is a PWM frame synchronizing signal and said second signal is a video horizontal synchronizing signal.
Claim 10
Dependent Claim
124 words
A time division multiplexing transmission system as claimed in claim 5, wherein said synchronizing information of said digital synchronizing signal is formed by a pulse modulation frame synchronizing signal of a fixed pattern, said first and second control signals are formed by a mode control code, which mode control code comprises a code bit for indicating a coincidence of the digital synchronizing signal and the horizontal synchronizing signal, a code bit for indicating a coincidence of the digital synchronizing signal and the pulse modulation frame synchronizing signal, a code bit for indicating a coincidence of the digital synchronizing signal and a video vertical synchronizing signal and at least one code bit for representing the video signal transmission period or the audio signal transmission period.
Claim 11
Dependent Claim
40 words
A time division multiplexing transmission system as claimed in claim 9, wherein said pulse modulation frame synchronizing signal of a fixed pattern is constructed by a substantially regular pattern having paRtially irregular portions such as 001010 . . . 0100.
Claim 12
Dependent Claim
36 words
A time division multiplexing transmission system as claimed in claim 9, wherein said digital synchronizing signal is preceded by a blanking signal and in said blanking signal is inserted a pilot signal having a separable amplitude.
Claim 13
Dependent Claim
44 words
A time division multiplexing transmission system as claimed in claim 1, wherein said given integer ratio at a time rate of which said first and second information signals are transmitted in turns is made equal to an integer ratio of a television frame period.
Claim 14
Dependent Claim
31 words
A time division multiplexing transmission system as claimed in claim 1, wherein said second frequency of said second signal is made equal to a horizontal synchronizing frequency of a television signal.
Claim 15
Dependent Claim
38 words
A time division multiplexing transmission system as claimed in claim 1, wherein said given frequency of said original signal has a relation of an integer ratio with respect to a color sub-carrier frequency of a color television signal.
Claim 16
Dependent Claim
358 words
A transmitter for use in the time division multiplexing transmission system for transmitting first and second information signals in turns at a time rate of a given integer ratio, said first and second information signals being divided at periods of first and second signals, respectively as claimed in claim 1, comprises a signal generator for producing an original signal having a given frequency; a first circuit for producing said first signal having a first frequency which is equal to a fraction of an integer of said given frequency of said original signal; a second circuit for producing said second signal having a second frequency which has a relation of an integer ratio with respect to said first frequency; a third circuit for producing a third signal having a third frequency which is equal to fractions of integers of said first and second frequencies; a fourth circuit for producing a fourth signal having a fourth frequency which is equal to a fraction of an integer of said third frequency; a gate circuit for alternately passing said first and second signals at a time rate of said given integer ratio under a control of a gate signal formed by said fourth signal; and a digital synchronizing signal generator which is triggered by an output signal from said gate circuit and produces a digital synchronizing signal composed of a synchronizing information consisting of a pulse chain of a given repetition frequency and first and second control signals each consisting of a pulse chain, pulses of which pulse chain appear at given time slots in synchronism with occurrence instances of said first, second and third signals, said synchronizing information of the given repetition frequency being of the common waveform in both of said first and second signal periods, but said first control signal in said first signal period being different from said second control signal in said second signal period; whereby said synchronizing information and first control signal are inserted in said first information signal divided at said first signal period and said synchronizing information and second control signal are inserted in said second information signal divided at said second signal period.
Claim 17
Dependent Claim
23 words
A transmitter as claimed in claim 15, wherein each of said first, second, third and fourth circuits is constructed by a frequency divider.
Claim 18
Dependent Claim
200 words
A transmitter as claimed in claim 15, wherein said digital synchronizing signal generator is formed by a shift register having a plurality of parallel input terminals, a series input terminal, a series output terminal and a parallel enable terminal for changing a mode of said shift register so as to permit parallel inputs; to parallel input terminals for setting the synchronizing information is supplied a fixed input signal corresponding to said pulse chain of said synchronizing information; to parallel input terminals for setting said control signal are supplied said first, second and third signals, separatEly; to said parallel enable terminal is supplied the output signal from said gate circuit; and to said series input terminal is supplied said original signal of said given frequency; whereby said first or second signal supplied to said parallel input terminal is written in said shift register and the content in the shift register is driven by said original signal of the given frequency supplied to said series input terminal so as to produce from said series output terminal a pulse chain forming said synchronizing information and a pulse chain forming said first or second control signal at the given period of said original signal.
Claim 19
Dependent Claim
102 words
A transmitter as claimed in claim 16, wherein said shift register comprises at least five parallel input terminals for setting said control signal, to a first parallel input terminal is connected an output of said second frequency divider, to a second parallel input terminal is connected an output of said first frequency divider, to a third parallel input terminal is connected an output of said third frequency divider, to a fourth parallel input terminal is connected an output of said fourth frequency divider through an inverter and to a fifth parallel input terminal is connected said output of said fourth frequency divider.
Claim 20
Dependent Claim
435 words
A transmitter for use in the transmission system as claimed in claim 14, wherein said transmitter comprises a signal generator for producing an original signal having a given frequency; a first circuit for producing said first signal having a first frequency which is equal to a fraction of an integer of said given frequency of said original signal; a second circuit for producing said second signal having a second frequency which has a relation of an integer ratio with respect to said first frequency; a third circuit for producing a third signal having a third frequency which is equal to fractions of integers of said first and second frequencies; a fourth circuit for producing a fourth signal having a fourth frequency which is equal to a fraction of an integer of said third frequency; a gate circuit for alternately passing said first and second signals at a time rate of said given integer ratio under a control of a gate signal formed by said fourth signal; a digital synchronizing signal generator which is triggered by an output signal from said gate circuit and produces a digital synchronizing signal composed of a synchronizing information consisting of a pulse chain of a given repetition frequency and first and second control signals each consisting of a pulse chain, pulses of which pulse chain appear at given time slots in synchronism with occurrence instances of said first, second and third signals, said synchronizing information of the given repetition frequency being of the common waveform in both of said first and second signal periods, but said first control signal which is produced in said first signal period being different from said second control signal which is produced in said second signal period; whereby said synchronizing information and first control signal are inserted in said first information signal divided at said first signal period and said synchronizing information and second control signal are inserted in said second information signal divided at said second signal period, a synchronizing signal generator for producing said color sub-carrier, a horizontal driving signal and a vertical driving signal in synchronism with an external color television signal supplied to said synchronizing signal generator; and a reset pulse generator for receiving said horizontal and vertical driving signals and producing reset pulses for resetting said first and third circuits; whereby said color sub-carrier is supplied to said signal generator so as to produce said original signal of the given frequency which has a relation of an integer ratio with respect to said color sub-carrier frequency and said first and second signals are locked to said external color telEvision signal.
Claim 21
Dependent Claim
272 words
A receiver for use in the time division multiplexing transmission system as claimed in claim 1 for transmitting first and second information signals in turns at a time rate of a given integer ratio, said first and second information signals being divided at periods of first and second signals, respectively and said first information signal being transmitted together with a synchronizing information composed of a pulse chain having a given repetition frequency and a first control signal and said second information signal being transmitted together with said synchronizing information and a second control signal, comprises means for extracting said pulse chain having the given repetition frequency from said synchronizing information of the common waveform inserted in said first and second information signals which have been transmitted in turns at a time rate of said given integer ratio and producing clock pulses having a repetition frequency which is equal to said repetition frequency of said extracted pulse chain; means for extracting said first and second control signals on the basis of the produced clock pulses; and means for forming first and second synchronizing signals having said first and second frequencies, respectively, from said clock pulses; whereby said first and second synchronizing signals and said extracted first and second control signals are collated to each other and said means for forming said first and second synchronizing signals is controlled by a collation output so as to produce said first and second synchronizing signals of said first and second frequencies, respectively, in synchronism with a transmitted signal and said first and second information signals are reproduced by means of said first and second synchronizing signals.
Claim 22
Dependent Claim
452 words
A receiver as claimed in claim 20, wherein said means for forming said first and second synchronizing signals of said first and second frequencies comprises a first synchronizing signal generating circuit and a second synchronizing signal generating circuit, these circuits being connected in parallel to said clock pulse producing means; said first synchronizing signal generating circuit comprises a first gate connected to said clock pulse producing means, a first synchronizing signal generator having a counter for counting the clock pulses passed through said first gate and producing a signal of said first frequency and a forward and backward synchronization protector which detects a coincidence between said first control signal from said control signal extracting means and said output signal from said first synchronizing signal generator and produces such conditioning signals to said first gate that in an asynchronous condition of said first synchronizing signal said first gate is always opened until said synchronization protector detects a given number of successive coincidences, after the synchronization protector has detected said given number of successive coincidences, said first gate is opened only for the digital synchronizing signal period in the transmitted signal so as to establish a synchronous condition of the first synchronizing signal and after the synchronous condition has been established, said first gate is opened only for the digital synchronizing signal period unless said synchronization protector detects a given number of successive discordances between said first control signal and said output signal from said first synchronizing signal generator; and said second synchronizing signal generating circuit comprises a second gate connected to said clock pulse producing means, a second synchronizing signal generator having a counter for counting the clock pulses passed through said second gate and producing an output signal of said second frequency and a backward synchronization protector which detects a coincidence between said second control signal from said control signal extracting means and said output signal from said second synchronizing signal and Produces such conditioning signals to said second gate that said second gate is always opened before said backward synchronization protector detects said coincidence, after the backward synchronization protector detects said coincidence said second gate is opened only for the digital synchronizing signal period in the transmitted signal so as to establish a synchronous condition of the second synchronizing signal and after the synchronous condition has been established, said second gate is opened only for the digital synchronizing signal period unless said backward synchronization protector detects a given number of successive discordances between said second control signal and said output signal from said second synchronizing signal generator; whereby said first and second synchronizing signal generating circuits are made operative simultaneously so as to generate said first and second synchronizing signals independently.
Claim 23
Dependent Claim
173 words
A receiver as claimed in claim 21, wherein there is provided an AND gate between said control signal extracting means and said second gate in said second synchronizing signal generating circuit and to said AND gate are connected the output of said forward and backward synchronization protector and the output of said control signal extracting means, from which output terminal is supplied said second control signal; whereby said second gate is always closed until the synchronous condition is established and when the synchronization condition of said first synchronizing signal is established, said second gate is opened only for the digital synchronizing signal period by means of said output signal from said forward and backward synchronization protector and said second control signal through said AND gate so as to establish the synchronous condition in such a manner that at first the synchronous condition of said first synchronizing signal is settled and the synchronous condition of said second synchronizing signal is established immediately after said synchronous condition of the first synchronizing signal has been completed.
Claim 24
Dependent Claim
328 words
A receiver as claimed in claim 21, wherein there is further provided in parallel with said first and second synchronizing signal generating circuits a digital synchronizing signal generating circuit which comprises a third gate connected to said clock pulse producing means, a digital synchronizing signal generator having a counter for counting the clock pulses passed through said third gate and producing a digital signal which has said first frequency in the first information signal transmission period and said second frequency in the second information signal transmission period, respectively and a forward and backward synchronization protector which detects a coincidence between said digital synchronizing signal from said generator and said digital synchronizing signal in the transmission signal and produces such conditioning signal to said third gate that in an asynchronous condition of said digital synchronizing signal said third gate is always opened, after said forward and backward synchronization protector has detected a given number of successive coincidences, said third gate is opened only for the digital synchronizing signal period in a transmitted signal so as to established a synchronous condition of said digital synchronizing signal and after the synchronous condition has been established, said third gate is opened only for said digital synchronizing signal unless said forward and backward synchronization protector detects a given number of successive discordances between said digital synchronizing signal generated from said digital synchronizing signal generator and the digital synchronizing signal in the transmitted signal; the output of said forward and backward synchronization protector is connected to said first and second gates; whereby before the synchronous condition of the digital synchronizing signal is established said first and second gates are always closed and after said synchronous condItion has been established said first and second gates are opened only for the digital synchronizing signal period so as to produce said first and second synchronizing signals in synchronism with the transmitted signal; and further said forward and backward synchronization protector has only a backward synchronization protecting function.
Claim 25
Dependent Claim
122 words
A receiver as claimed in claim 21 wherein said forward and backward synchronization protector comprises a first AND gate for detecting said coincidences; a second AND gate for detecting said discordances; a coincidence counter for counting said coincidences and producing an output coincidence signal when it counts said given number of successive coincidences; a discordance counter for counting said discordances and producing an output discordance signal when it counts said given number of successive discordances; and a third AND gate for receiving said output synchronizing signal from said synchronizing signal generator and said output discordance signal and producing said conditioning signal, whereby said discordance counter and said coincidence counter are reset by said output coincidence signal and said output discordance signal, respectively.
Claim 26
Dependent Claim
89 words
A receiver as claimed in claim 21, wherein said backward synchronization protector comprises a first AND gate for detecting said discordances; a discordance counter for counting said discordances and producing an output discordance signal when it counts said given number of successive discordances; a second AND gate for detecting said coincidence and supplying said coincidence as a reset signal to said discordance counter; and a third AND gate for receiving said synchronizing signal generated from said synchronizing signal generator and said output discordance signal and producing said conditioning signal.
Claim 27
Dependent Claim
143 words
A receiver as claimed in claim 20, wherein said means for extracting said control signal comprises a shift register having a plurality of stages, the number of which is at least equal to the number of bits forming said digital synchronizing signal in the transmitted signal, the successive bits of the digital synchronizing signal of the transmitted signal being written in said successive stages of said shift register; a coincidence detector having comparison input terminals connected to given stages of said shift register corresponding to the synchronizing information of the given pattern and reference input terminals connected to given potentials in accordance with said given pattern of said synchronizing information; and a gate circuit having one input terminal connected to the output of said coincidence detector and other input terminals connected to given stages of said shift register corresponding to said control signal.
Claim 28
Dependent Claim
122 words
A receiver as claimed in claim 20, wherein said means for producing the clock pulses comprises a gate for receiving the input transmitted signal; a phase comparator connected to an output of said gate; a sample-hold circuit connected to said phase comparator; and a controlled oscillator for producing said clock pulses, said clock pulses generated from said oscillator being fedback to said phase comparator which produces an output corresponding to a phase error between the input signal and said clock pulses, whereby in the asynchronous condition said gate and sample-hold circuit are made always operative and after the synchronous condition has been established, said gate and sample-hold circuit is made operative only for the digital synchronizing signal period of the transmitted signal.
Claim 29
Dependent Claim
184 words
A receiver as claimed in claim 23, wherein said digital synchronizing signal generator comprises a counter for counting the clock pulses; and a coincidence detector for comparing the content of said counter with a reference signal; whereby in the first information signal transmission period said reference signal for said coincidence detector is of a first reference signal under the control of said first control signal and when the content of said counter coincidences with said first reference signal, said coincidence detector produces an output signal, by means of which the count value of said counter is jumped by a given amount so as to produce an output signal of said first frequency and in the second information signal transmission period said reference signal is of a second reference signal under the control of said second control signal and when the content of said counter coincides with said second reference signal, said coincidence circuit produces an output signal, by means of which the count value of said counter is jumped by a given amount so as to produce an output signal of said second frequency.
Claim 30
Dependent Claim
259 words
A receiver as claimed in claim 20, wherein said means for extracting first and second synchronizing signal comprises a first gate connected to said clock pulse generating means and having one gate terminal connected to said control signal extracting means; a second gate having one input terminal connected to said first gate; a first counter connected to said second gate and for counting clock pulses passed through said first and second gates; a third gate connected to said first counter; a second counter connected to said third gate and for counting the clock pulses passed through said first gate; a fourth gate having input terminals connected to output terminals of said first and second counters and an output terminal connected to the other input terminal of said second gate; and a synchronization protector having an input terminal connected to an output of said second counter and an output terminal connected to the other gate terminal of said first gate; whereby at first said second gate is made opened, but said third gate is made closed so that said first counter counts a given number of the clock pulses, and when said first counter reaches its count up condition, said second gate is made closed through said fourth gate and at the same time said third gate is made opened so that said second counter starts to count the clock pulses, and further said second counter produces said first synchronizing signal in said first information signal transmission period and said second synchronizing signal in said second information signal transmission period.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-09 | 1978-06-10 | 1978-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-09 | 1982-06-10 | 1982-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-09 | 1986-06-10 | 1986-12-10 | $7700.00 | Window Closed / Lapsed |