Method of making a semi planar insulated gate field-effect transistor device with implanted field

Claim 1

A METHOD FOR TREATING A SEMICONDUCTOR BODY FOR FORMING A DEVICE REGION WITHIN SAID BODY SUITABLE FOR MANUFACTURING AT LEAST ONE MOS STRUCTURE THEREWITHIN INCLUDING A GATE OXIDE ELEMENT, AND FOR FORMING A FIELD REGION SURROUNDING SAD DEVICE REGION HAVING HIGH FIELD INVERSION VOLTAGE CHARACTERISTIC COMPRISING THE STEPS OF: PROVIDING A BODY OF SEMICONDUCTOR MATERIAL OF ONE TYPE CONDUCTIVITY AND SAID BODY HAVING AN UPPER SURFACE; FORMING A FIRST OXIDE LAYER ON SAID UPPER SURFACE OF SAID BODY OF SEMICONDUCTOR MATERIAL, AND SAID LAYER IS FORMED BY THERMAL OXIDATION RESULTING IN THE FORMATION OF A LAYER SUITABLE FOR USE AS THE GATE OXIDE ELEMENT OF THE MOS STRUCTURE; DEPOSITING A FIRST MAKING LAYER ON SAID FIRST OXIDE LAYER, AND SAID LAYER IS SUITABLE FOR USE BOTH AS A MASK AGAINST IMPLANTING IONS INTO SAID BODY OF SEMICONDUCTOR MATERIAL AND FOR USE AS A MASK AGAINST THERMAL OXIDATION OF THE UNDERLYING PORTION OF THE UPPER SURFACE OF SAID BODY OF SEMICONDUCTOR MATERIAL; FORMING A SECOND OXIDE LAYER ON SAID FIRST MASKING LAYER; PATTERNING SAID SECOND OXIDE LAYER FOR RETAINING A PORTION OF SAID SECOND OXIDE LAYER OVERLYING A CORRESPONDING PORTION OF SAID INTERVENING MASKING LAYER AND OVERLYING A CORRESPONDING PORTION OF SAID FIRST OXIDE LAYER SUITABLE AS THE GATE ELEMENT AND ALSO OVERLYING THE DEVICE PORTION OF SAID UPPER SURFACE OF SAID SEMICONDUCTOR BODY IN WHICH THE MOS STRUCTURE IS TO BE FORMED, AND SAID PATTERNING ALSO BEING OPERATIVE FOR EXPOSING THE REMAINING PORTIONS OF SAID MASKING LAYER; ETHCABLY REMOVING SAID EXPOSED PORTION OF SAID FIRST MASKING LAYER FOR EXPOSING THE UNDERLYING PORTIONS OF SAID FIRST OXIDE LAYER, IMPLANTING IMPURITY IONS OF SAID ONE CONDUCTIVITY TYPE THROUGH SAID EXPOSED PORTION OF SAID FIRST OXIDE LAYER INTO SAID BODY OF SEMICONDUCTOR MATERIAL TO FORM AN IMPLANTED FIELD REGION UNDER SAID EXPOSED PORTION OF SAID FIRST OXIDE LAYER, AND SAID IMPURITY IONS FORMING A FIELD REGION OF SAID ONE TYPE CONDUCTIVITY AND SAID FIELD REGION BEING POSITIONED TO SURROUND A PORTION OF SAID SEMICONDUCTOR BODY; HEATIN SAID RESULTING BODY OF SEMICONDUCTOR MATERIAN IN AN INERT ATMOSPHERE FOR REDISTRIBUTING SAID IMPURITY IONS DEEPER INTO SAID BODY; FURTHER HEATING SAID BODY OF SEMICONDUCTOR MATERIAN IN AN OXIDIZING ATMOSPHERE FOR OXIDIZING THE UPPER SURFACE OF SAID BODY UNDERLYING THE EXPOSED PORTION OF SAID FIRST OXIDE LAYER RESULTING IN SUCH AN INCREASE IN THE THICKNESS OF SAID EXPOSED OXIDE LAYER AS TO BE SUITABLE AS A FIELD OXIDE LAYER OVER SAID UPPER SURFACE OF SAID BODY OF SEMICONDUCTOR MATERIAL NOT MASKED BY SAID MASKING LAYER WHEREBY, THE MASKED PORTION OF SAID FIRST OXIDE LAYER IS SUITABLE FOR USE AS THE GATE OXIDE ELEMENT OF THE MOS STRUCTURE AND THE IMPLANTED FIELD REGION INCREASES THE FIELD SURFACE INVERSION VOLTAGE CHARACTERISTIC OF THE SEMICONDUCTOR STRUCTURE AND THE FIELD OXIDE LAYER PROVIDES A MORE EVEN SURFACE FOR THE RESULTING SEMICONDUCTOR BODY.

Claim 2

A METHOD FOR TREATING A SEMICONDUCTOR BODY FOR FORMING A DEVICE REGION WITHIN SAID BODY SUITABLE FOR MANUFACTURING AT LEAST ONE MOS STRUCTURE THEREWITHIN INCLUDING A GATE OXIDE ELEMENT, AND FOR FORMING A FIELD REGION SURROUNDING SAD DEVICE REGION HAVING HIGH FIELD INVERSION VOLTAGE CHARACTERISTIC COMPRISING THE STEPS OF: PROVIDING A BODY OF SEMICONDUCTOR MATERIAL OF ONE TYPE CONDUCTIVITY AND SAID BODY HAVING AN UPPER SURFACE; FORMING A FIRST OXIDE LAYER ON SAID UPPER SURFACE OF SAID BODY OF SEMICONDUCTOR MATERIAL, AND SAID LAYER IS FORMED BY THERMAL OXIDATION RESULTING IN THE FORMATION OF A LAYER SUITABLE FOR USE AS THE GATE OXIDE ELEMENT OF THE MOS STRUCTURE; DEPOSITING A FIRST MAKING LAYER ON SAID FIRST OXIDE LAYER, AND SAID LAYER IS SUITABLE FOR USE BOTH AS A MASK AGAINST IMPLANTING IONS INTO SAID BODY OF SEMICONDUCTOR MATERIAL AND FOR USE AS A MASK AGAINST THERMAL OXIDATION OF THE UNDERLYING PORTION OF THE UPPER SURFACE OF SAID BODY OF SEMICONDUCTOR MATERIAL; FORMING A SECOND OXIDE LAYER ON SAID FIRST MASKING LAYER; PATTERNING SAID SECOND OXIDE LAYER FOR RETAINING A PORTION OF SAID SECOND OXIDE LAYER OVERLYING A CORRESPONDING PORTION OF SAID INTERVENING MASKING LAYER AND OVERLYING A CORRESPONDING PORTION OF SAID FIRST OXIDE LAYER SUITABLE AS THE GATE ELEMENT AND ALSO OVERLYING THE DEVICE PORTION OF SAID UPPER SURFACE OF SAID SEMICONDUCTOR BODY IN WHICH THE MOS STRUCTURE IS TO BE FORMED, AND SAID PATTERNING ALSO BEING OPERATIVE FOR EXPOSING THE REMAINING PORTIONS OF SAID MASKING LAYER; ETHCABLY REMOVING SAID EXPOSED PORTION OF SAID FIRST MASKING LAYER FOR EXPOSING THE UNDERLYING PORTIONS OF SAID FIRST OXIDE LAYER, IMPLANTING IMPURITY IONS OF SAID ONE CONDUCTIVITY TYPE THROUGH SAID EXPOSED PORTION OF SAID FIRST OXIDE LAYER INTO SAID BODY OF SEMICONDUCTOR MATERIAL TO FORM AN IMPLANTED FIELD REGION UNDER SAID EXPOSED PORTION OF SAID FIRST OXIDE LAYER, AND SAID IMPURITY IONS FORMING A FIELD REGION OF SAID ONE TYPE CONDUCTIVITY AND SAID FIELD REGION BEING POSITIONED TO SURROUND A PORTION OF SAID SEMICONDUCTOR BODY; HEATIN SAID RESULTING BODY OF SEMICONDUCTOR MATERIAN IN AN INERT ATMOSPHERE FOR REDISTRIBUTING SAID IMPURITY IONS DEEPER INTO SAID BODY; FURTHER HEATING SAID BODY OF SEMICONDUCTOR MATERIAN IN AN OXIDIZING ATMOSPHERE FOR OXIDIZING THE UPPER SURFACE OF SAID BODY UNDERLYING THE EXPOSED PORTION OF SAID FIRST OXIDE LAYER RESULTING IN SUCH AN INCREASE IN THE THICKNESS OF SAID EXPOSED OXIDE LAYER AS TO BE SUITABLE AS A FIELD OXIDE LAYER OVER SAID UPPER SURFACE OF SAID BODY OF SEMICONDUCTOR MATERIAL NOT MASKED BY SAID MASKING LAYER WHEREBY, THE MASKED PORTION OF SAID FIRST OXIDE LAYER IS SUITABLE FOR USE AS THE GATE OXIDE ELEMENT OF THE MOS STRUCTURE AND THE IMPLANTED FIELD REGION INCREASES THE FIELD SURFACE INVERSION VOLTAGE CHARACTERISTIC OF THE SEMICONDUCTOR STRUCTURE AND THE FIELD OXIDE LAYER PROVIDES A MORE EVEN SURFACE FOR THE RESULTING SEMICONDUCTOR BODY.

Claim 8

A method for treating a semiconductor body for forming a plurality of device regions within said body suitable for manufacturing at least one MOS structure within each region including a gate oxide element, and for forming a field region surrounding said device regions having a high field inversion voltage characteristic for preventing surface channeling between devices, comprising the steps of: providing a body of semiconductor material of one type conductivity and said body having an upper surface; forming a first oxide layer on said upper surface of said body of semiconductor material, and said layer is formed by thermal oxidation resulting in the formation of a layer suitable for use as the gate oxide element of the MOS structure; depositing a first masking layer on said first oxide layer, and said layer is suitable for use both as a mask against implanting ions into said body of semiconductor material and for use as a mask against thermal oxidation of the underlying portions of the upper surface of said body of semiconductor material; forming a second oxide layer on said first masking layer; patterning said second oxide layer for retaining a plurality of portions of said second oxide layer overlying first and second corresponding portions of said intervening masking layer and overlying first and second corresponding portions of said first oxide layer suitable as the gate element of the MOS devices and also overlying first and second device portions of said upper surface of said semiconductor body in which the MOS structure is to be formed, and said patterning also being operative for exposing the remaining portions of said masking layer; etchably removing selected portions of said first masking layer for exposing the underlying portions of said first oxide layer, and a first one of said portions of said first oxide layer being associated with said first device region and a second one of said portions of said first oxide layer being associated with said second device region and said etching also being operative for retaining said first and second portions of said masking layer being in encircling relationship with said exposed, corresponding portions of said first oxide layer; providing an ion implant mask for at least one of said exposed portions of said first oxide layer surrounding said second portion of said masking layer; implanting impurity ions through said remaining exposed portion of said first oxide layer into said body of semiconductor material to form an implanted field region of a second conductivity type under said exposed portion of said first oxide layer, and said impurity ions forming a field region of said second conductivity type, and said field region being positioned to surround a portion of said semiconductor body; heating said rsulting body of semiconductor material in an inert atmosphere for redistributing said impurity ions deeper into said body; further heating said body of semiconductor material in an oxidizing atmosphere for oxidizing the upper surface of said body underlying said exposed portions of said first oxide layer, which are exposed during said etching step, resulting in an increase in the thickness of said exposed oxide layer and the formation of a field oxide layer over said upper surface of said body of semiconductor material not masked by said masking layer; and removing said remaining portion of said second oxide layer and said first masking layer and said ion implant mask whereby, the masked portion of said first oxide layer is suitable for use as the gate oxide element of the MOS structure and the implanted field region increases tHe field surface inversion voltage characteristic of the semiconductor structure and the field oxide layer provides a more even surface for the resulting semiconductor body.

Claim 9

A method for treating a semiconductor body for forming a plurality of device regions within said body suitable for manufacturing at least one MOS structure within each region including a gate oxide element, and for forming a field region surrounding said device regions having a high field inversion voltage characteristic for preventing surface channeling between devices, comprising the steps of: providing a body of semiconductor material of one type conductivity and said body having an upper surface; forming a first oxide layer on said upper surface of said body of semiconductor material, and said layer is formed by thermal oxidation resulting in the formation of a layer suitable for use as the gate oxide element of the MOS structure; depositing a first masking layer on said first oxide layer, and said layer is suitable for use both as a mask against implanting ions into said body of semiconductor material and for use as a mask against thermal oxidation of the underlying portions of the upper surface of said body of semiconductor material; forming a second oxide layer on said first masking layer; patterning said second oxide layer for retaining a plurality of portions of said second oxide layer overlying first and second corresponding portions of said intervening masking layer and overlying first and second corresponding portions of said first oxide layer suitable as the gate element of the MOS devices and also overlying first and second device portions of said upper surface of said semiconductor body in which the MOS structure is to be formed, and said patterning also being operative for exposing the remaining portions of said masking layer; etchably removing selected portions of said first masking layer for exposing the underlying portions of said first oxide layer, and a first one of said portions of said first oxide layer being associated with said first device region and a second one of said portions of said first oxide layer being associated with said second device region and said etching also being operative for retaining said first and second portions of said masking layer being in encircling relationship with said exposed, corresponding portions of said first oxide layer; providing an ion implant mask for at least one of said exposed portions of said first oxide layer surrounding said second portion of said masking layer; implanting impurity ions through said remaining exposed portion of said first oxide layer into said body of semiconductor material to form an implanted field region of a second conductivity type under said exposed portion of said first oxide layer, and said impurity ions forming a field region of said second conductivity type, and said field region being positioned to surround a portion of said semiconductor body; heating said rsulting body of semiconductor material in an inert atmosphere for redistributing said impurity ions deeper into said body; further heating said body of semiconductor material in an oxidizing atmosphere for oxidizing the upper surface of said body underlying said exposed portions of said first oxide layer, which are exposed during said etching step, resulting in an increase in the thickness of said exposed oxide layer and the formation of a field oxide layer over said upper surface of said body of semiconductor material not masked by said masking layer; and removing said remaining portion of said second oxide layer and said first masking layer and said ion implant mask whereby, the masked portion of said first oxide layer is suitable for use as the gate oxide element of the MOS structure and the implanted field region increases tHe field surface inversion voltage characteristic of the semiconductor structure and the field oxide layer provides a more even surface for the resulting semiconductor body.