Return to zero detection circuit for variable data rate scanning

Claim 2

For use in a digital recording system wherein binary bits of information are stored in a return to zero format by a storage medium and wherein translational motion between a read head and the storage medium causes the read head to generate successive initial and subsequent distinguishable electric signals having a relative nature dependent upon the information content of a binary bit being read, a self-clocking information detection circuit connected to receive the electric signals from the read head, the detection circuit comprising an integrator connected to receive a read head electric signal and generate an integrated read head electric signal as an output; first and second detectors connected to detect positive and negative pulses respectively on the integrated read head electric signal, each detector including circuitry for initiating a predetermined detector output signal when a pulse of a polarity to which the detector is responsive exceeds a first predetermined magnitude and terminating a detector output pulse only when the pulse magniude is less than a second predetermined magnitude which is less than the first predetermined magnitude.

Claim 3

For use in a digital magnetic recording system wherein binary bits of information are stored in a return to zero format in which magnetization of a magnetic medium with a first polarity represents a first binary character and magnetization of a magnetic medium with a second polarity represents a second binary character and wherein a read head generates initial and subsequent successive electric pulses of opposite polarity in response to the reading of a bit stored on the magnetic medium with the relative polarity of the successive pulses being dependent upon the polarity of magnetization of a bit which is read, a self-clocking information detection circuit connected to receive the electric pulses from the read head, the detection circuit comprising an integrator connected to receive an electric read head pulse as an input and generate the time integral of the read head pulse as an integrated output signal; a peak detector circuit connected to detect peak magnitudes of thE integrated output signal and generate a reference signal having a magnitude proportional thereto; and a detector circuit connected to the reference signal and the integrated output signal, the detector circuit generating a first detector output signal whenever the integrated output signal is of a first polarity and has a magnitude greater than the magnitude of the reference signal and generating a second detector output signal whenever the integrated output signal is of a second polarity opposite the first polarity and has a magnitude greater than the magnitude of the reference signal.

Claim 4

For use in a digital magnetic recording system wherein binary bits of information are stored in a return to zero format in which magnetization of a magnetic medium with a first polarity represents a first binary character and magnetization of a magnetic medium with a second polarity represents a second binary character and wherein a read head generates initial and subsequent successive electric pulses of opposite polarity in response to the reading of a bit stored on the magnetic medium with the relative polarity of the successive pulses being dependent upon the polarity of magnetization of a bit which is read, a self-clocking information detection circuit connected to receive the electric pulses from the read head, the detection circuit comprising an integrator connected to receive an electric read head pulse as an input and generate the time integral of the read head pulse as an integrated output signal; a peak detector circuit connected to detect peak magnitudes of thE integrated output signal and generate a reference signal having a magnitude proportional thereto; and a detector circuit connected to the reference signal and the integrated output signal, the detector circuit generating a first detector output signal whenever the integrated output signal is of a first polarity and has a magnitude greater than the magnitude of the reference signal and generating a second detector output signal whenever the integrated output signal is of a second polarity opposite the first polarity and has a magnitude greater than the magnitude of the reference signal.

Claim 5

For use in a digital magnetic recording system wherein binary bits of information are stored in a return to zero format in which magnetization of a magnetic medium with a first polarity represents a first binary character and magnetization of a magnetic medium with a second polarity represents a second binary character and wherein a read head generates initial and subsequent successive electric pulses of opposite polarity in response to the reading of a bit stored on the magnetic medium with the relative polarity of the successive pulses being dependent upon the polarity of magnetization of a bit which is read, a self-clocking information detection circuit connected to receive the electric pulses from the read head, the detection circuit comprising an integrator connected to receive the electric pulses and generate an integrated read signal indicative of the integral of the electric pulses, and at least one amplitude detector connected to the integrator and generating an output signal when the integrated read signal has a selected polarity and exceeds a selected magnitude, the magnitude of the integrated read signal increasing beyond the selected magnitude in response to an initial electric pulse and decreasing below the selected magnitude in response to a subsequent electric pulse.

Claim 6

For use in a digital magnetic recording system wherein binary bits of information are stored in a return to zero format in which magnetization of a magnetic medium with a first polarity represents a first binary character and magnetization of a magnetic medium with a second polarity represents a second binary character and wherein a read head generates initial and subsequent successive electric pulses of opposite polarity in response to the reading of a bit stored on the magnetic medium with the relative polarity of the successive pulses being dependent upon the polarity of magnetization of a bit which is read, a self-clocking information detection circuit connected to receive the electric pulses from the read head, the detection circuit comprising an integrator connected to receive the electric pulses and generate an integrated read signal indicative of the integral of the electric pulses, and at least one amplitude detector connected to the integrator and generating an output signal when the integrated read signal has a selected polarity and exceeds a selected magnitude, the magnitude of the integrated read signal increasing beyond the selected magnitude in response to an initial electric pulse and decreasing below the selected magnitude in response to a subsequent electric pulse.

Claim 7

For use in a digital magnetic recording system wherein binary bits of information are stored in a return to zero format in which magnetization of a magnetic medium with a first polarity represents a first binary character and magnetization of a magnetic medium with a second polarity represents a second binary character and wherein a read head generates initial and subsequent successive electric pulses of opposite polarity in response to the reading of a bit stored on the magnetic medium with the relative polarity of the successive pulses being dependent upon the polarity of magnetization of a bit which is read, a self-clocking information detection circuit connected to receive the electric pulses from the read head, the detection circuit comprising an amplitude detector connected to receive the electric pulses and generate first and second output signals in response to respective first and second opposite polarity electric pulses exceeding first and second selected magnitudes respectively; and a demodulator logical circuit connected to receive the first and second output signals, the demodulator circuit generating a binary output signal in response to an amplitude detector output signal and terminating the output signal in response to a different amplitude detector output signal, the demodulator circuit output signal being of a first type when generated in response to a first amplitude detector output signal and of a second type when generated in response to a second amplitude detector output signal.

Claim 8

For use in a digital magnetic recording system wherein binary bits of information are stored in a return to zero format in which magnetization of a magnetic medium with a first polarity represents a first binary character and magnetization of a magnetic medium with a second polarity represents a second binary character and wherein a read head generates initial and subsequent successive electric pulses of opposite polarity in response to the reading of a bit stored on the magnetic medium with the relative polarity of the successive pulses being dependent upon the polarity of magnetization of a bit which is read, a self-clocking information detection circuit connected to receive the electric pulses from the read head, the detection circuit comprising an amplitude detector connected to receive the electric pulses and generate first and second output signals in response to respective first and second opposite polarity electric pulses exceeding first and second selected magnitudes respectively; and a demodulator logical circuit connected to receive the first and second output signals, the demodulator circuit generating a binary output signal in response to an amplitude detector output signal and terminating the output signal in response to a different amplitude detector output signal, the demodulator circuit output signal being of a first type when generated in response to a first amplitude detector output signal and of a second type when generated in response to a second amplitude detector output signal.

Claim 9

The detection circuit as set forth in claim 4 above wherein the demodulator circuit includes first and second flip-flops having set, reset outputs A, A and B, B respectively, wherein output A is the first type of demodulator circuit output signal and wherein output B is the second type of demodulator circuit output signal.

Claim 10

The detection circuit as set forth in claim 5 above wherein the first flip-flop is connected to be set in response to a first amplitude detector output signal when both the first and second flip-flops are in a reset condition, wherein the first flip-flop is coNnected to be reset in response to a second amplitude detector output signal when the first flip-lop is in a set condition, wherein the second flip-flop is connected to be set in response to a second amplitude detector output signal when both the first and second flip-flops are in a reset condition and wherein the second flip-flop is connected to be reset in response to a first amplitude detector output signal when the second flip-flop is in a set condition.

Claim 11

A self-clocking circuit for detecting bits of digital information stored on a magnetic medium in a return to zero format in which a first polarity of magnetization represents a first binary character and an opposite polarity of magnetization represents a second binary character comprising: a read head positionable adjacent the magnetic medium providing an electric signal indicative of flux changes encountered during relative translational motion between the read head and the magnetic medium, said electric signal including first and second successive pulses of first and opposite polarities in response to leading and trailing edge, respectively of a stored bit with the polarity of the first pulse being dependent upon the polarity of magnetization of the storage medium at a character position being read; and a detection circuit connected to receive the electric signal, the detection circuit generating a first output signal in response to a first pulse of one polarity, generating a second output signal in response to a first pulse of a polarity opposite the one polarity, and discontinuing generating of the output signal in response to a second pulse. 9at each termination of a first detector output signal and at each termination of a second detector output signal; second and third J-K flip-flops, each connected to assume a new state dependent upon the states of J and K inputs thereto at each occurrence of the clock signal, the second flip-flop having J, K inputs JA, JK respectively and set, reset outputs A, A respectively, the third flip-flop having J, K inputs JB, KB respectively and set, reset outputs, B, B respectively and logic circuitry connected to drive the second and third flip-flop inputs in accordance with the logical functions JA AB, KA ABN, JB ABN, and KB ABP. a detection circuit connected to receive the electric signal, the detection circuit generating a first output signal in response to a first pulse of one polarity, generating a second output signal in response to a first pulse of a polarity opposite the one polarity, and discontinuing generating of the output signal in response to a second pulse.

Claim 12

A self-clocking circuit for detecting bits of digital information stored on a magnetic medium in a return to zero format in which a first polarity of magnetization represents a first binary character and an opposite polarity of magnetization represents a second binary character comprising: a read head positionable adjacent the magnetic medium providing an electric signal indicative of flux changes encountered during relative translational motion between the read head and the magnetic medium, said electric signal including first and second successive pulses of first and opposite polarities in response to leading and trailing edge, respectively of a stored bit with the polarity of the first pulse being dependent upon the polarity of magnetization of the storage medium at a character position being read; and a detection circuit connected to receive the electric signal, the detection circuit generating a first output signal in response to a first pulse of one polarity, generating a second output signal in response to a first pulse of a polarity opposite the one polarity, and discontinuing generating of the output signal in response to a second pulse. 9at each termination of a first detector output signal and at each termination of a second detector output signal; second and third J-K flip-flops, each connected to assume a new state dependent upon the states of J and K inputs thereto at each occurrence of the clock signal, the second flip-flop having J, K inputs JA, JK respectively and set, reset outputs A, A respectively, the third flip-flop having J, K inputs JB, KB respectively and set, reset outputs, B, B respectively and logic circuitry connected to drive the second and third flip-flop inputs in accordance with the logical functions JA AB, KA ABN, JB ABN, and KB ABP. a detection circuit connected to receive the electric signal, the detection circuit generating a first output signal in response to a first pulse of one polarity, generating a second output signal in response to a first pulse of a polarity opposite the one polarity, and discontinuing generating of the output signal in response to a second pulse.

Claim 13

A data detection circuit connected to receive an electric read signal from a read head of a digital magnetic recording system wherein the reading of a first character induces a positive initial pulse and a negative subsequent pulse on the read signal and the reading of a second character induces a negative initial pulse and a positive subsequent pulse on the read signal, the detection circuit comprising an amplitude detector connected to detect positive and negative excursions of the electric read signal beyond selected magnitudes chosen to permit detection of initial and subsequent pulses and generate first and second output signals in response to positive and negative excursions respectively; and a digital logic demodulator circuit connected to generate first and second detector circuit output signals indicative of information read by the read head, the first detection circuit output signal being intitiated by an initial amplitude detector output signal when there is no detection circuit output signal and terminated by a subsequent second amplitude detector output signal and the second detection circuit output signal being initiated by a second amplitude detector output signal when there is no detection circuit output signal and terminated by a subsequent first amplitude detector output signal.

Claim 14

A data detection circuit connected to receive an electric read signal from a read head of a digital magnetic recording system wherein the reading of a first character induces a positive initial pulse and a negative subsequent pulse on the read signal and the reading of a second character induces a negative initial pulse and a positive subsequent pulse on the read signal, the detection circuit comprising an amplitude detector connected to detect positive and negative excursions of the electric read signal beyond selected magnitudes chosen to permit detection of initial and subsequent pulses and generate first and second output signals in response to positive and negative excursions respectively; and a digital logic demodulator circuit connected to generate first and second detector circuit output signals indicative of information read by the read head, the first detection circuit output signal being intitiated by an initial amplitude detector output signal when there is no detection circuit output signal and terminated by a subsequent second amplitude detector output signal and the second detection circuit output signal being initiated by a second amplitude detector output signal when there is no detection circuit output signal and terminated by a subsequent first amplitude detector output signal.

Claim 15

The information detection circuit as set foRth in claim 1 above, wherein the first detector comprises a high gain differential amplifier having a positive input, a negative input coupled to a reference voltage of the first predetermined magnitude and an output; a first resistance coupling the positive input to the read head integrated electric signal; and a second resistance coupling the output of the differential amplifier to the positive input thereof.

Claim 16

The detection circuit as set forth in claim 2 above, further comprising a digital logic circuit including a first asynchronous flip-flop having a set input coupled to the first detector output signal, a reset input connected to the second detector output signal, a set condition output signal P and a reset condition output signal N; a clocking circuit connected to generate a clocking signal at each termination of a first detector output signal and at eaCh termination of a second detector output signal; second and third J-K flip-flops, each connected to assume a new state dependent upon the states of J and K inputs thereto at each occurrence of the clock signal, the second flip-flop having J, K inputs JA, KA respectively and set, reset outputs A, A respectively, the third flip-flop having J, K inputs JB, KB respectively and set, reset outputs, B, B respectively; and logic circuitry connected to drive the second and third flip-flop inputs in accordance with the logical functions JA ABP, KA ABN, JB ABN, and KB ABP.