Patent US3852688A successfully refreshed from Google Patents.
US3852688A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor circuit
Assignee: Sony Corp
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Filing: 1973-08-09
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Granted: 1974-12-03
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Expires: 1993-08-09
Abstract
Abstract First and second pairs of transistors of opposite conductivity types are connected so that the emitter of each transistor of one conductivity type is connected to the emitter of a transistor of the opposite conductivity type. The collectors of the first pair of transistors of the first conductivity type are connected to a load which in turn is connected to a power supply terminal. The collectors of the other pair of transistors of the opposite conductivity type are connected by way of a common impedance to another terminal of the power supply. A first signal source provides opposite polarity signals to input terminals of a differential amplifier, the outputs of which are connected to inputs of the firstpair of transistors. The transfer characteristic between the signal source and the first pair of transistors is logarithmic. A similar differential amplifier logarithmic circuit is supplied by a second signal source and in turn supplies the other pair of transistors. The circuit arrangement provides a balanced output signal which is a product of only the first and second signals in the load, and this output signal is linear in relationship to the first and second input signals.
Inventors
- 👤 M Takeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:05
CPC Classifications
H; H03; H03C; H03C1/00; H03C1/52; H03C1/54; H03C1/542; H03C1/545; H03C2200/00; H03C2200/0004; H03C2200/0012; H03C2200/0037; H03C2200/0079
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
236 words
A transistor circuit comprising: A. a first pair of transistors comprising first and second transistors of one conductivity type, each having base, emitter, and collector electrodes; B. a second pair of transistors comprising third and fourth transistors of the opposite conductivity type and each having base, emitter and collector electrodes; C. a load impedance, the collector electrodes of said first pair of transistors being connected thereto, said load impedance being connected in series between said collector electrodes of said first pair of transistors and a power supply terminal to receive direct current from said terminal; D. means for connecting the emitter electrodes of said first and second transistors to the emitter electrodes of said third and fourth transistors, respectively, the collector electrodes of said third and fourth transistors being connected to a second power supply terminal; E. a first pair of converter circuits, each having a logarithmic input-output characteristic and being connected to the base electrodes of said first pair of transistors respectively; F. a second pair of converter circuits, each having a logarithmic input-output characteristic and being connected to the base electrodes of said second pair of transistors respectively; G. a first input signal source for supplying a first pair of opposite polarity signals to said first pair of converter circuits; and H. a second input signal source for supplying a second pair of opposite polarity signals to the other of said pairs of converters.
Claim 2
Dependent Claim
236 words
A transistor circuit comprising: A. a first pair of transistors comprising first and second transistors of one conductivity type, each having base, emitter, and collector electrodes; B. a second pair of transistors comprising third and fourth transistors of the opposite conductivity type and each having base, emitter and collector electrodes; C. a load impedance, the collector electrodes of said first pair of transistors being connected thereto, said load impedance being connected in series between said collector electrodes of said first pair of transistors and a power supply terminal to receive direct current from said terminal; D. means for connecting the emitter electrodes of said first and second transistors to the emitter electrodes of said third and fourth transistors, respectively, the collector electrodes of said third and fourth transistors being connected to a second power supply terminal; E. a first pair of converter circuits, each having a logarithmic input-output characteristic and being connected to the base electrodes of said first pair of transistors respectively; F. a second pair of converter circuits, each having a logarithmic input-output characteristic and being connected to the base electrodes of said second pair of transistors respectively; G. a first input signal source for supplying a first pair of opposite polarity signals to said first pair of converter circuits; and H. a second input signal source for supplying a second pair of opposite polarity signals to the other of said pairs of converters.
Claim 3
Dependent Claim
31 words
fifteenth and sixteenth transistors connected in a fourth series connection between the collector of said eighth transistor and said first-named power supply terminal and being symmetrical with said third series connection.
Claim 4
Dependent Claim
31 words
fifteenth and sixteenth transistors connected in a fourth series connection between the collector of said eighth transistor and said first-named power supply terminal and being symmetrical with said third series connection.
Claim 5
Dependent Claim
102 words
eleventh and twelfth transistors connected in a second series connection between the collector of said sixth transistor and said second power supply terminal and being symmetrical with said first series connection; D. said seventh and eighth transistors are of the opposite conductivity type from said second pair of transistors, and the emitter electrodes of said seventh and eighth transistors are connected together. E. said transistor circuit comprises, in addition, a second constant current circuit connected in series between said second power supply terminal and said emitter electrodes of said seventh and eighth transistors; and F. said second pair of diode circuits comprises;
Claim 6
Dependent Claim
102 words
eleventh and twelfth transistors connected in a second series connection between the collector of said sixth transistor and said second power supply terminal and being symmetrical with said first series connection; D. said seventh and eighth transistors are of the opposite conductivity type from said second pair of transistors, and the emitter electrodes of said seventh and eighth transistors are connected together. E. said transistor circuit comprises, in addition, a second constant current circuit connected in series between said second power supply terminal and said emitter electrodes of said seventh and eighth transistors; and F. said second pair of diode circuits comprises;
Claim 7
Dependent Claim
27 words
a second pair of diode circuits connected in the collector circuits of said seventh and eighth transistors, respectively, and comprising load circuits for said second differential amplifier.
Claim 8
Dependent Claim
27 words
a second pair of diode circuits connected in the collector circuits of said seventh and eighth transistors, respectively, and comprising load circuits for said second differential amplifier.
Claim 9
Dependent Claim
36 words
a first pair of diode circuits connected in the collector circuits of said fifth and sixth transistors, respectively, and comprising load circuits for said first differential amplifier; and B. said second pair of coNverter circuits comprises:
Claim 10
Dependent Claim
36 words
a first pair of diode circuits connected in the collector circuits of said fifth and sixth transistors, respectively, and comprising load circuits for said first differential amplifier; and B. said second pair of coNverter circuits comprises:
Claim 11
Dependent Claim
17 words
The transistor circuit according to claim 1 in which: A. said first pair of converter circuits comprises:
Claim 12
Dependent Claim
36 words
The transistor circuit according to claim 2 in which said second signal source comprises a variable voltage supply circuit connected to said third and fourth pairs of transistors to control the gain of said transistor circuit.
Claim 13
Dependent Claim
79 words
The transistor circuit according to claim 2 in which: A. said fifth and sixth transistors are of the opposite conductivity type from said first pair of transistors, and the emitter electrodes of said fifth and sixth transistors are connected together; B. said transistor circuit comprising, in addition, a first constant current circuit connected in series between said first-named power supply terminal and said emitter electrodes of said fifth and sixth transistors; C. said first pair of diode circuits comprises:
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-02 | 1978-06-03 | 1978-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-02 | 1982-06-03 | 1982-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-02 | 1986-06-03 | 1986-12-03 | $7700.00 | Window Closed / Lapsed |