US3852677A
Expired / Lapsed
US
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Demodulator
Assignee: Compteurs Schlumberger SA
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Filing: 1973-06-28
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Granted: 1974-12-03
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Expires: 1993-06-28
Abstract
Abstract Disclosed is a demodulator for pulses modulated by signals at a determined frequency and comprising: A BISTABLE MEMORY RECEIVING SIGNALS ON ITS RESET INPUT, THE OUTPUT OF THIS FIRST COUNTER BEING CONNECTED TO THE SECOND CONTROL INPUT OF THE BISTABLE MEMORY, A SECOND COUNTER WHOSE RESET CONTROL INPUT IS CONNECTED TO THE OUTPUT OF THE BISTABLE MEMORY.
Inventors
- 👤 C Neuville
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:44
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H02; H02J; H02J13/00; H02J13/13; H02J13/1311; H02J13/1313; H04; H04B; H04B3/00; H04B3/54; H04B2203/00; H04B2203/54; H04B2203/5404; H04B2203/5416; Y; Y02; Y02E; Y02E60/00; Y04; Y04S; Y04S40/00; Y04S40/12; Y04S40/121
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
265 words
A demodulator for producing a delayed output signal in response to an input signal of the type including a pulse which has been modulated at a predetermined frequency and consisting of a limited train of pulse signals at the predetermined frequency comprising bistable circuit means for receiving the input signal and for changing from a first state to a second state in response to the beginning of the first pulse of the train of pulse signals; a source of clock pulses; first counter means for receiving and counting clock pulses from said source and for producing a reset output signal when the count accumulated thereby reaches a predetermined total; first circuit means for coupling said reset output signal from said first counter means to said bistable circuit means to return said bistable circuit means to said first state; second circuit means for coupling the train of pulse signals in said input signal to said first counter means to reset said first counter means and restart the counting of clock pulses in response to each pulse received thereby; second counter means for receiving and counting clock pulses from said source and for producing the delayed output signal representative of the arrival of an input signal, said second counter means being operative to initiate said output pulse after a preselected number of clock pulses has been counted by said second counter means; and third circuit means connected between said bistable circuit means and said second counter means for providing to said second counter means a reset signal when said bistable circuit means returns to said first state.
Claim 2
Dependent Claim
265 words
A demodulator for producing a delayed output signal in response to an input signal of the type including a pulse which has been modulated at a predetermined frequency and consisting of a limited train of pulse signals at the predetermined frequency comprising bistable circuit means for receiving the input signal and for changing from a first state to a second state in response to the beginning of the first pulse of the train of pulse signals; a source of clock pulses; first counter means for receiving and counting clock pulses from said source and for producing a reset output signal when the count accumulated thereby reaches a predetermined total; first circuit means for coupling said reset output signal from said first counter means to said bistable circuit means to return said bistable circuit means to said first state; second circuit means for coupling the train of pulse signals in said input signal to said first counter means to reset said first counter means and restart the counting of clock pulses in response to each pulse received thereby; second counter means for receiving and counting clock pulses from said source and for producing the delayed output signal representative of the arrival of an input signal, said second counter means being operative to initiate said output pulse after a preselected number of clock pulses has been counted by said second counter means; and third circuit means connected between said bistable circuit means and said second counter means for providing to said second counter means a reset signal when said bistable circuit means returns to said first state.
Claim 3
Dependent Claim
40 words
A demodulator according to claim 1 wherein the count time of said first counter means is at least equal to the time defined by two cycles of the said signals, but shorter than the duration of the input signal pulses.
Claim 4
Dependent Claim
39 words
A demodulator according to claim 2 wherein the count time of said second counter means is longer than the count time of the first counter and equal to a fraction of the minimum duration of said input signal pulse.
Claim 5
Dependent Claim
230 words
A demodulator for producing a delayed output signal in response to an input signal of the type including a pulse which has been modulated at a predetermined frequency and consisting of a limited train of pulse signals at the predetermined frequency comprising: a threshold circuit for receiving the input signal and for delivering shaped signals having amplitude values at least equal to the value of the threshold, a bistable memory circuit having a first control input connected to the output of said threshold circuit and a second control input; a clock pulse source; first counter circuit means for counting pulses from said source, said circuit means having a reset input connected to the output of said threshold circuit, the output of said first Counter being connected to said second control input of said bistable memory, the count time of said first counter being at least equal to the time defined by two cycles of the train of pulse signals, but shorter than the duration of the input signal; and second counter circuit means for counting pulses from said source, said second counter circuit means having a reset control input connected to the reset output of said bistable memory, the count time of said second counter being longer than the count time of the said first counter and equal to a fraction of the minimum duration of the input signal pulse.
Claim 6
Dependent Claim
230 words
A demodulator for producing a delayed output signal in response to an input signal of the type including a pulse which has been modulated at a predetermined frequency and consisting of a limited train of pulse signals at the predetermined frequency comprising: a threshold circuit for receiving the input signal and for delivering shaped signals having amplitude values at least equal to the value of the threshold, a bistable memory circuit having a first control input connected to the output of said threshold circuit and a second control input; a clock pulse source; first counter circuit means for counting pulses from said source, said circuit means having a reset input connected to the output of said threshold circuit, the output of said first Counter being connected to said second control input of said bistable memory, the count time of said first counter being at least equal to the time defined by two cycles of the train of pulse signals, but shorter than the duration of the input signal; and second counter circuit means for counting pulses from said source, said second counter circuit means having a reset control input connected to the reset output of said bistable memory, the count time of said second counter being longer than the count time of the said first counter and equal to a fraction of the minimum duration of the input signal pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-02 | 1978-06-03 | 1978-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-02 | 1982-06-03 | 1982-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-02 | 1986-06-03 | 1986-12-03 | $7700.00 | Window Closed / Lapsed |