Patent US3852575A successfully refreshed from Google Patents.
US3852575A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Strappable inactivity timer for data set
Assignee: MI Inc
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Filing: 1973-03-21
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Granted: 1974-12-03
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Expires: 1993-03-21
Abstract
Abstract A timer which monitors the inactivity of a data set for clearing and disconnecting an inactive data terminal from connection to another terminal transmission line network after a selected inactivity period has elapsed. A binary timer is reset by the presence of data and a carrier. Selectable combinations of timer output may be strapped to a decoder to permit selection of the inactivity period.
Inventors
- 👤 L Daniels
- 👤 R Fretwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:19
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/02
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
252 words
A strappable inactivity timer for a data set, said data set being connected to a 60 Hz power source and having a carrier detector, the timer comprising: a. a strapping terminal board haVing a plurality of adjacent, non-conductively connected, associated terminal pairs which are selectively connectable; b. a multiple stage binary counter having a trigger input connected to 60 Hz pulses from said power source and having outputs of selected stages connected to one of each of said associated terminal pairs; c. a first AND gate logic means having its output connected to a reset input of said counter having a first input connected to said carrier detector and a second input connected to the data set circuit at a node where communicated data pulses occur, for resetting said counter in response to the presence of a carrier and of data bits; and d. decoding means having inputs connected to the other terminal of each of said associated pairs and an output connected to a clear circuit of said data set for clearing said data set in response to actuation of all of stages of said counter to which the inputs of said decoder means are selectively connected. e. an OR gate having one input connected to a source of transmitted data bits and another input connected to a source of received data bits; f. a differentiator circuit with its input connected to the output of said OR gate and its output connected to said second input of said first AND gate.
Claim 2
Dependent Claim
252 words
A strappable inactivity timer for a data set, said data set being connected to a 60 Hz power source and having a carrier detector, the timer comprising: a. a strapping terminal board haVing a plurality of adjacent, non-conductively connected, associated terminal pairs which are selectively connectable; b. a multiple stage binary counter having a trigger input connected to 60 Hz pulses from said power source and having outputs of selected stages connected to one of each of said associated terminal pairs; c. a first AND gate logic means having its output connected to a reset input of said counter having a first input connected to said carrier detector and a second input connected to the data set circuit at a node where communicated data pulses occur, for resetting said counter in response to the presence of a carrier and of data bits; and d. decoding means having inputs connected to the other terminal of each of said associated pairs and an output connected to a clear circuit of said data set for clearing said data set in response to actuation of all of stages of said counter to which the inputs of said decoder means are selectively connected. e. an OR gate having one input connected to a source of transmitted data bits and another input connected to a source of received data bits; f. a differentiator circuit with its input connected to the output of said OR gate and its output connected to said second input of said first AND gate.
Claim 3
Dependent Claim
31 words
An inactivity timer according to claim 1 wherein said decoding means comprises a diode-transistor-logic second AND gate having a plurality of diode inputs each connected to one of said other terminals.
Claim 4
Dependent Claim
58 words
An inactivity timer according to claim 2 wherein said second decoding AND gate comprises a transistor having a control input resistively coupled to a source for biasing the transistor in a conducting state, wherein said diodes connect said control input to each of said other terminals and wherein said transistor controls the clear contacts of a clear relay.
Claim 5
Dependent Claim
38 words
An inactivity timer according to claim 2 wherein said counter comprises a 16 stage counter and wherein the outputs of the last four stages corresponding to the four most significant digits are connected to said strapping terminal board.
Claim 6
Dependent Claim
62 words
An inactivity timer according to claim 1 wherein said second AND gate comprises a transistor having a control input resistively coupled to a source for biasing the transistor in a conducting state, wherein said diodes of said second AND gate connect said control input to each of said other terminals and wherein said transistor controls the clear contacts of a clear relay.
Claim 7
Dependent Claim
39 words
An inactivity timer according to claim 5 wherein said counter comprises a 16 stage binary counter and wherein the outputs of the last four stages corresponding to the four most significant digits are connected to said strapping terminal board.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-02 | 1978-06-03 | 1978-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-02 | 1982-06-03 | 1982-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-02 | 1986-06-03 | 1986-12-03 | $7700.00 | Window Closed / Lapsed |