Adaptive phase synchronizer

Claim 1

An adaptive phase synchronizing system for synchronizing the phase of a received digital signal having a plurality of bits, each bit having a predetermined bit interval, to correspond to the phase of a local clock, said system comprising: means for receiving said digital signal; sample and storage means connected to said receiving means for taking a predetermined number, n, of samples of said received digital signal during each bit interval, said sample and storage means including a shift register having n + 1 stages for storing said samples; n modulo 2 adders, each having two inputs connected to a different pair of adjacent ones of said n + 1 stages, and an output, each of said modulo 2 adders being responsive to the samples stored in the stages connected thereto to provide a transition signal when the last mentioned samples are unequal; a counter connected to the output of each of said modulo 2 adders, said counter being responsive to said transition signals for providing an error signal when more than one transition signal is simultaneously provided by said modulo 2 adders; accumulator means coupled to the output of each of said modulo 2 adders, said accumulator means being responsive to said modulo 2 adder means for a predetermined sampling period once during each bit interval for counting the number of transition signals provided by each of said modulo 2 adders and providing a count signal having a value representative of said number of transition signals provided by each one of the modulo 2 adders, said accumulator means including means for reducing the value of each of said count signals corresponding to the modulo 2 adders not providing transition signals during said predetermined sampling period; switch means connected to said accumulator means and said counter, said switch means being responsive to said counter for rendering said accumulator means non-responsive to said modulo 2 adders for the predetermined sampling period concurrent with the presence of said error signal, or the absence of a transition from 0 to 1 or from 1 to 0; majority logic means connected to said accumulator means and responsive to the accumulator means having the highest value count signal to provide a sample identifying signal at an output terminal thereof for identifying one of said n samples having a transition adjacent thereto; delay means connected to said sample and storage means for receiving and delaying said samples; variable phase shifting means connected to said delay means for receiving delayed samples therefrom, said variable phase shifting means including a shift register having a second predetermined number, p, of stages greater than the predetermined number, n; logic means coupled to said majority logic means and said variable phase shifting means for selecting n adjacent ones of said p stages in response to said sample identifying signal; and data generating means coupled to said n adjacent ones of said p stages selected by said logic means, said data generating means being responsive to the samples present in one of said selected n stages for generating one data bit in response to said last mentioned samples during each bit interval of said received digital signal.

Claim 7

A system for synchronizing the phase of a received digital signal having a plurality of bits, each bit having a predetermined bit interval, to correspond to the phase of a local clock, said system comprising: means for receiving said digital signals; sample and storage means connected to said receiving means for taking a predetermined number of samples of each bit of said digital signal, said sample and storage means having a plurality of stages including a first stage and a last stage for storing said samples, the number of said stages exceeding said predetermined number of samples taken of each bit by one, said sample and storage means including means responsive to said local clock for shifting said samples between said stages from said first stage to said last stage thereof; comparison means connected to each of said stages of said sample and storage means for comparing the contents of said stages, said comparison means including means responsive to unlike contents in adjacent stages of said sample and storage means for providing a transition signal indicative of each transition of information between adjacent stages; counting means connected to said comparison means for counting the number of transitions present simultaneously in said sample and storage means; accumulator means responsive to transition signals for a predetermined period once during each bit interval for counting the number of transitions of information between each pair of adjacent stages during the receipt of said digital signals and for storing a count signal representative of the number of transitions of information between each pair of adjacent stages, said accumulator means including means for increasing the count signals upon the occurrence of a transition of information between adjacent stages and for reducing the count signals in the absence of a transition of information; switch means connected to said comparison means, said accumulator means and said counting means, said switch means being responsive to said counting means to make said accumulator means non-responsive to said transition signals whenever the number of transitions present simultaneously in said sample and storage means is zero or exceeds one: majority logic means connected to said accumulator means and responsive thereto for providing a location signal representative of the pair of stages having the highest number of transitions therebetween during the receipt of said digital signals; delay means having an input connected to said sample and storage means for receiving said samples, and an output; and variable phase shifting means connected to the output of said delay means for receiving said samples and to said majority logic means, said variable phase shifting means including means for shifting the phase of said samples by a predetermined amount over a predetermined range in excess of one bit interval in accordance with the pair of stages having the highest number of transitions.

Claim 8

A system for synchronizing the phase of a received digital signal having a plurality of bits, each bit having a predetermined bit interval, to correspond to the phase of a local clock, said system comprising: means for receiving said digital signals; sample and storage means connected to said receiving means for taking a predetermined number of samples of each bit of said digital signal, said sample and storage means having a plurality of stages including a first stage and a last stage for storing said samples, the number of said stages exceeding said predetermined number of samples taken of each bit by one, said sample and storage means including means responsive to said local clock for shifting said samples between said stages from said first stage to said last stage thereof; comparison means connected to each of said stages of said sample and storage means for comparing the contents of said stages, said comparison means including means responsive to unlike contents in adjacent stages of said sample and storage means for providing a transition signal indicative of each transition of information between adjacent stages; counting means connected to said comparison means for counting the number of transitions present simultaneously in said sample and storage means; accumulator means responsive to transition signals for a predetermined period once during each bit interval for counting the number of transitions of information between each pair of adjacent stages during the receipt of said digital signals and for storing a count signal representative of the number of transitions of information between each pair of adjacent stages, said accumulator means including means for increasing the count signals upon the occurrence of a transition of information between adjacent stages and for reducing the count signals in the absence of a transition of information; switch means connected to said comparison means, said accumulator means and said counting means, said switch means being responsive to said counting means to make said accumulator means non-responsive to said transition signals whenever the number of transitions present simultaneously in said sample and storage means is zero or exceeds one: majority logic means connected to said accumulator means and responsive thereto for providing a location signal representative of the pair of stages having the highest number of transitions therebetween during the receipt of said digital signals; delay means having an input connected to said sample and storage means for receiving said samples, and an output; and variable phase shifting means connected to the output of said delay means for receiving said samples and to said majority logic means, said variable phase shifting means including means for shifting the phase of said samples by a predetermined amount over a predetermined range in excess of one bit interval in accordance with the pair of stages having the highest number of transitions.