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US3849774A Expired / Lapsed US ⏱️ 0.0 years remaining

Analog-to-digital converter employing an electromagnetic resolver

Assignee: ASTROSYST Inc
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Filing: 1972-09-14
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Granted: 1974-11-19
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Expires: 1992-09-14
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Abstract

Abstract An analog-to-digital converter system for generating a highresolution digital output corresponding to the position of a rotatable shaft by the use of digital techniques and components. The system employs a resolver having a receiver coupled to compensating and rotor windings thereof for providing a digital output corresponding to the angular position of the rotor with respect to the compensating winding. Excitation voltages are applied to the two input windings of the resolver by a voltage generator comprising an autotransformer having a plurality of sinusoidally distributed taps, a first switching unit for applying a voltage of appropriate polarity across the autotransformer and a second switching unit for coupling voltages at the taps of the autotransformer to the resolver input windings. The voltages applied across the resolver input windings have fundamental frequency components which are precisely in phase quadrature and have low harmonic content.

Inventors

  • 👤 S Barth

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 21:30
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/64; H03M1/645

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 911 words
In an analog-to-digital converter system including an electromagnetic transducer having first and second reference windings, a voltage generator for providing stepped voltages to said first and second reference windings, said voltages having fundamental sinusoidal frequency components in phase quadrature with respect to each other and low harmonic content, comprising an impedance element having first and second ends and having at least first and second groups of spaced taps thereon, first switching means connected to said impedance element for alternately connecting reference voltages of opposite polarity and constant value across said first and second groups of spaced taps, said taps being located on said impedance element to provide a voltage at each tap within a group which is a sinusoidal function of said location with respect to a tap maintained at a fixed potential, said first switching means further comprising an input terminal and first, second, third and fourth output terminals, a clock generator for generating pulses, a counter having an input coupled to said clock generator and a first output coupled to said first switching means, said counter resetting after receiving a predetermined number of pulses from said clock generator, a decoder having an input coupled to a second output of said counter and a plurality of output terminals, each of said output terminals being coupled to the control terminals of a corresponding tap switch in said first and second groups, said decoder energizing sequentially said tap switches in accordance with pulses received by said counter means from said clock generator, said first switching means further comprising a first multivibrator having an input coupled to the input terminal of said first switching means and a pair of outputs coupled to said first and second output terminals of said first switching means, said first multivibrator receiving a pulse each time said counter resets and reversing the states of the voltages at its first and second outputs, a second multivibrator having an input coupled to an output of said first multivibrator and a pair of outputs, said second multivibrator reversing the states of the voltages at its outputs for every second pulse received by said first multivibrator, first and second switching elements each having an input coupled to a corresponding output of said second multivibrator and an output coupled to said third and fourth output terminals of said first switching means and to a corresponding end of said impedance element, said first and second switching elements being driven alternately into conduction each time the output of said second multivibrator changes states, second switching means connected to said impedance element and having first and second output terminals, said second switching means coupling sequentially and selectively the taps in each of said first and second groups Respectively to said first and second output terminals to provide stepped output voltages thereat, said voltages having fundamental sinusoidal components in phase quadrature with each other, said second switching means including first and second groups of said tap switches, each tap switch having a first terminal, a second terminal and a control terminal, the first terminal of each of the switches in said first and second groups being coupled to a corresponding tap in said first and second groups of spaced taps respectively; and a switching circuit having a first input terminal coupled to the second terminals of said first group of tap switches and a second input terminal coupled to the second terminals of said second group of tap switches, said switching circuit further comprising third and fourth input terminals coupled to the first and second output terminals of said first switching means, first, second, third, fourth, fifth and sixth switches, each of said switches having first, second and control electrodes, the control electrodes of said first, third and fifth switches being coupled to the third input terminal of said switching circuit and said second, fourth and sixth switches being coupled to the fourth input terminal of said switching circuit, means coupling the second and first electrodes of said first and second switches respectively to the second input terminal of said switching circuit and means coupling the second and first electrodes of said third and fourth switches respectively to the first input terminal of said switching circuit, first, second and third operational amplifiers, each of said amplifiers having first and second input terminals and an output terminal; the first input terminal of said first amplifier being coupled to the first electrode of said first switch and the second electrode of said fourth switch, the second input terminal and the output terminal of said first amplifier being coupled together; the first input terminal of said second amplifier being coupled to the second electrode of said fifth switch and the first electrode of said sixth switch, the second input terminal of said second amplifier being coupled to the first electrode of said fifth switch, the second input and output terminals of said third amplifier and the output terminal of said second amplifier; and the first input terminal of said third amplifier being coupled to the second electrode of said second switch and the first electrode of said third switch, the second electrode of said sixth switch being coupled to a reference point, means coupling the outputs of said first and second amplifiers to the second and first output terminals respectively of said second switching means, and means coupling the first and second output terminals of said second switching means to the first and second input windings of said transducer respectively.
Claim 2
Dependent Claim 911 words
In an analog-to-digital converter system including an electromagnetic transducer having first and second reference windings, a voltage generator for providing stepped voltages to said first and second reference windings, said voltages having fundamental sinusoidal frequency components in phase quadrature with respect to each other and low harmonic content, comprising an impedance element having first and second ends and having at least first and second groups of spaced taps thereon, first switching means connected to said impedance element for alternately connecting reference voltages of opposite polarity and constant value across said first and second groups of spaced taps, said taps being located on said impedance element to provide a voltage at each tap within a group which is a sinusoidal function of said location with respect to a tap maintained at a fixed potential, said first switching means further comprising an input terminal and first, second, third and fourth output terminals, a clock generator for generating pulses, a counter having an input coupled to said clock generator and a first output coupled to said first switching means, said counter resetting after receiving a predetermined number of pulses from said clock generator, a decoder having an input coupled to a second output of said counter and a plurality of output terminals, each of said output terminals being coupled to the control terminals of a corresponding tap switch in said first and second groups, said decoder energizing sequentially said tap switches in accordance with pulses received by said counter means from said clock generator, said first switching means further comprising a first multivibrator having an input coupled to the input terminal of said first switching means and a pair of outputs coupled to said first and second output terminals of said first switching means, said first multivibrator receiving a pulse each time said counter resets and reversing the states of the voltages at its first and second outputs, a second multivibrator having an input coupled to an output of said first multivibrator and a pair of outputs, said second multivibrator reversing the states of the voltages at its outputs for every second pulse received by said first multivibrator, first and second switching elements each having an input coupled to a corresponding output of said second multivibrator and an output coupled to said third and fourth output terminals of said first switching means and to a corresponding end of said impedance element, said first and second switching elements being driven alternately into conduction each time the output of said second multivibrator changes states, second switching means connected to said impedance element and having first and second output terminals, said second switching means coupling sequentially and selectively the taps in each of said first and second groups Respectively to said first and second output terminals to provide stepped output voltages thereat, said voltages having fundamental sinusoidal components in phase quadrature with each other, said second switching means including first and second groups of said tap switches, each tap switch having a first terminal, a second terminal and a control terminal, the first terminal of each of the switches in said first and second groups being coupled to a corresponding tap in said first and second groups of spaced taps respectively; and a switching circuit having a first input terminal coupled to the second terminals of said first group of tap switches and a second input terminal coupled to the second terminals of said second group of tap switches, said switching circuit further comprising third and fourth input terminals coupled to the first and second output terminals of said first switching means, first, second, third, fourth, fifth and sixth switches, each of said switches having first, second and control electrodes, the control electrodes of said first, third and fifth switches being coupled to the third input terminal of said switching circuit and said second, fourth and sixth switches being coupled to the fourth input terminal of said switching circuit, means coupling the second and first electrodes of said first and second switches respectively to the second input terminal of said switching circuit and means coupling the second and first electrodes of said third and fourth switches respectively to the first input terminal of said switching circuit, first, second and third operational amplifiers, each of said amplifiers having first and second input terminals and an output terminal; the first input terminal of said first amplifier being coupled to the first electrode of said first switch and the second electrode of said fourth switch, the second input terminal and the output terminal of said first amplifier being coupled together; the first input terminal of said second amplifier being coupled to the second electrode of said fifth switch and the first electrode of said sixth switch, the second input terminal of said second amplifier being coupled to the first electrode of said fifth switch, the second input and output terminals of said third amplifier and the output terminal of said second amplifier; and the first input terminal of said third amplifier being coupled to the second electrode of said second switch and the first electrode of said third switch, the second electrode of said sixth switch being coupled to a reference point, means coupling the outputs of said first and second amplifiers to the second and first output terminals respectively of said second switching means, and means coupling the first and second output terminals of said second switching means to the first and second input windings of said transducer respectively.
Claim 3
Dependent Claim 53 words
Apparatus as defined by claim 1 wherein the second input terminal of said second amplifier is coupled to the first electrode of said fifth switch and the second input and output terminals of said third amplifier through a first resistor and to the output terminal of said second amplifier through a second resistor.
Claim 4
Dependent Claim 49 words
Apparatus as defined by claim 1 wherein the means coupling the outputs of said first and second amplifiers to the second and third output terminals of said second switching means comprises first and second filter means respectively, said filter means further reducing the harmonic content of said stepped voltages.
Claim 5
Dependent Claim 450 words
An analog-to-digital converter system comprising an electromagnetic transducer having at least first and second reference windings, an output winding and means for changing the relative position of said output winding with respect to said input windings; a clock generator; an impedance element having first and second groups of sinusoidally distributed taps thereon; a plurality of tap switches, each of said switches having a first terminal coupled to a corresponding tap on said impedaNce element, a second terminal and a control terminal; first counter means having an input coupled to said clock generator, said first counter means resetting after receiving a predetermined number of pulses from said clock generator; first switching means having an input terminal coupled to a first output of said first counter means for receiving a pulse each time said first counter means resets and first, second, third and fourth output terminals, the voltage states at said first and second output terminals reversing when each pulse is received from said first counter means and the voltage states at said third and fourth output terminals reversing when every second pulse is received from said first counter means, said third and fourth output terminals being coupled across said impedance element; decoder means having an input coupled to a second output of said first counter means and a plurality of output terminals, each of said output terminals being coupled to the control terminals of a corresponding tap switch in each of said first and second groups, said decoder means energizing sequentially said tap switches in accordance with pulses received by said first counter means from said clock generator; a switching circuit having first, second, third and fourth input terminals and first and second output terminals, the third and fourth input terminals of said switching circuit being coupled to the first and second output terminals of said switching means, the first and second input terminals of said switching circuit being coupled to the second terminals of the tap switches coupled to the first and second groups of taps on said impedance element respectively and the first and second output terminals being coupled to the first and second reference windings respectively of said transducer, the voltage magnitudes at said first and second output terminals of said switching circuit corresponding to the voltages at the taps of said impedance element and the relative phase of the fundamental frequency components of said voltages being determined by the voltages at the first and second output terminals of said first switching means; and receiver means coupled to a reference winding and the output winding of said transducer for providing a digital output corresponding to the angular position of said rotor winding with respect to said reference winding.
Claim 6
Dependent Claim 450 words
An analog-to-digital converter system comprising an electromagnetic transducer having at least first and second reference windings, an output winding and means for changing the relative position of said output winding with respect to said input windings; a clock generator; an impedance element having first and second groups of sinusoidally distributed taps thereon; a plurality of tap switches, each of said switches having a first terminal coupled to a corresponding tap on said impedaNce element, a second terminal and a control terminal; first counter means having an input coupled to said clock generator, said first counter means resetting after receiving a predetermined number of pulses from said clock generator; first switching means having an input terminal coupled to a first output of said first counter means for receiving a pulse each time said first counter means resets and first, second, third and fourth output terminals, the voltage states at said first and second output terminals reversing when each pulse is received from said first counter means and the voltage states at said third and fourth output terminals reversing when every second pulse is received from said first counter means, said third and fourth output terminals being coupled across said impedance element; decoder means having an input coupled to a second output of said first counter means and a plurality of output terminals, each of said output terminals being coupled to the control terminals of a corresponding tap switch in each of said first and second groups, said decoder means energizing sequentially said tap switches in accordance with pulses received by said first counter means from said clock generator; a switching circuit having first, second, third and fourth input terminals and first and second output terminals, the third and fourth input terminals of said switching circuit being coupled to the first and second output terminals of said switching means, the first and second input terminals of said switching circuit being coupled to the second terminals of the tap switches coupled to the first and second groups of taps on said impedance element respectively and the first and second output terminals being coupled to the first and second reference windings respectively of said transducer, the voltage magnitudes at said first and second output terminals of said switching circuit corresponding to the voltages at the taps of said impedance element and the relative phase of the fundamental frequency components of said voltages being determined by the voltages at the first and second output terminals of said first switching means; and receiver means coupled to a reference winding and the output winding of said transducer for providing a digital output corresponding to the angular position of said rotor winding with respect to said reference winding.
Claim 7
Dependent Claim 80 words
An analog-to-digital converter system as defined by claim 4 wherein said receiver means comprises zero cross-over detecting means coupled to the reference and output windings of said transducer for providing signals at the instants the voltages across said windings reverse polarity, and second counter means coupled to said zero cross-over detecting means and said clock generator for producing a digital output signal corresponding to the interval between cross-overs of the voltages across the reference and output windings of said transducer.
Claim 8
Dependent Claim 18 words
An apparatus as defined by claim 4 wherein the reference winding of said transducer comprises a compensating winding.
Claim 9
Dependent Claim 35 words
An apparatus as defined by claim 5 wherein a first divider is interposed between said clock generator and said first counter and a second divider is interposed between said clock generator and said second counter.
Claim 10
Dependent Claim 18 words
An apparatus as defined by claim 4 wherein said impedance element is an autotransformer having a tapped coil.
Claim 11
Dependent Claim 158 words
An apparatus as defined by claim 4 wherein said switching means comprises a first multivibrator having an input coupled to the input terminal and a pair of outputs coupled to the first and second output terminals of said switching means, said first multivibrator receiving a pulse each time said first counter means resets and reversing the states of the voltages at said first and second output terminals; a second multivibrator having an input coupled to an output of said first multivibrator and a pair of outputs, said second multivibrator reversing the states of the voltages at its outputs for every secoNd pulse received by said first multivibrator, and first and second switching elements each having an input coupled to a corresponding output of said second multivibrator and an output coupled to said third and fourth output terminals, said first and second switching elements being driven alternately into conduction each time the output of said second multivibrator changes state.
Claim 12
Dependent Claim 122 words
An apparatus as defined by claim 4 wherein said switching circuit comprises means coupling the voltages at the first and second input terminals of said switching circuit during the first and third quadrants of each cycle of said fundamental sinusoidal frequency component to the first and second output terminals thereof, means coupling the voltages at the first input terminal of said switching circuit during the second and fourth quadrants of each cycle of said fundamental sinusoidal frequency component to the second output terminal thereof, and means coupling the negative of the voltage at the second input terminal of said switching circuit during the second and fourth quadrants of each cycle of said fundamental sinusoidal frequency component to the first output terminal thereof.
Claim 13
Dependent Claim 299 words
Apparatus as defined by claim 4 wherein said switching circuit furtherin comprises first, second, third, fourth, fifth and sixth switches, each of said switches having first, second and control electrodes, the control electrodes of said first, third and fifth switches being coupled to the third input terminal of said switching circuit and said second, fourth and sixth switches being coupled to the fourth input terminal thereof, means coupling the second and first electrodes of said first and second switches respectively to the second input terminal of said switching circuit and means coupling the second and first electrodes of said third and fourth switches respectively to the first input terminal of said switching circuit, first, second and third operational amplifiers, each of said amplifiers having first and second input terminals and an output terminal; the first input terminal of said first amplifier being coupled to the first electrode of said first switch and the second electrode of said fourth switch, the second input terminal and the output terminal of said first amplifier being coupled together; the first input terminal of said second amplifier being coupled to the said electrode of said fifth switch and the first electrode of said sixth switch, the second input terminal of said second amplifier being coupled to the first electrode of said fifth switch, the second input and output terminals of said third amplifier and the output terminal of said second amplifier; and the first input terminal of said third amplifier being coupled to the second electrode of said second switch and the first electrode of said third switch, the second electrode of said sixth switch being coupled to said reference point, and means coupling the outputs of said first and second amplifiers to the second and first output terminals respectively of said switching circuit.
Claim 14
Dependent Claim 91 words
An analog-to-digital converter as defined by claim 4 wherein said receiver means comprises first and second zero cross-over detectors coupled to the output and reference windings respectively of said transducer; a latch circuit coupled to the output of said first detector, and second counter means coupled to said clock generator, the output of said second detector and the input of said latch circuit, said latch circuit providing at its output a digital signal corresponding to the interval between cross-overs of the voltages across the reference and output windings of said transducer.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-11-18 1978-05-20 1978-11-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-11-18 1982-05-20 1982-11-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-11-18 1986-05-20 1986-11-19 $7700.00 Window Closed / Lapsed

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