Patent US3849761A successfully refreshed from Google Patents.
US3849761A
Expired / Lapsed
US
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Communication system
Assignee: Mitsubishi Electric Corp
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Filing: 1972-03-31
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Granted: 1974-11-19
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Expires: 1992-03-31
Abstract
Abstract A threshold detector sorts each of a plurality of n-bit binary code blocks representative of redundantly encoded information into correct bits and, if present, a bit ambiguous as to information content. The latter bit is transformed into an erased word. The correct digits and erased word forming one signal sequence are registered in a shift register with a corresponding checking code. Upon detecting the erased word, a correction circuit responds to the checking code to calculate the original exact word for the erased word. The calculated word is substituted for the erased word in the register. Also the Markov type of information such as the bipolar code is similarly processed and the correction is accomplished by utilizing the nature of the information.
Inventors
- 👤 Y Sugiyama
- 👤 K Fujiwra
- 👤 S Hirasawa
- 👤 M Kasahara
- 👤 T Namekawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:21
CPC Classifications
H; H04; H04L; H04L1/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
354 words
A communications system comprising, a plurality of signal repeaters having a first signal repeater receptive of a transmitted signal, a sequence of repeaters receptive of an output signal from a previous repeater and a last repeater, said received signal corresponding to a sequence of information code blocks and at least one checking code block, each information code block being an n-bit binary coded word corresponding to a redundantly encoded piece of information selected from a subset of a set of all n-bit binary code words, and said checking code block being an n-bit binary code word selected from a subset of n-bit binary code words not including said subset of information code blocks, said last repeater comprising first detection means receptive of said signal to develop output signals corresponding to a binary one signal, binary zero signal or an ambiguous signal ambiguous as to logic content thereof, first memory means receptive of said first detector output signals for storing said first detector output signals therein, circuit means receptive of said first detector output signal corresponding to said ambiguous signal levels to store said first detector output signal and develop a first control signal in response thereto, a transformation circuit receptive of said first control signal and said first detector output signals stored in said first memory means for transforming under control of said first control signal an information code block having an ambiguous signal level into a transformed code block selected from a subset of n-bit binary code words not including information code blocks, second detection means receptive of said first detection means output signals from said code transformation circuit for detecting transformed code blocks and developing a second control signal in response thereto, second storage means receptive of said first detectioN means output signals from said code transformation circuit for storing said first detection means output signals therein, an error detecting and correcting circuit connected to said second storage means and receptive of said second control signal for replacing said transformed code block with a correct information code block, and output means connected to said second storage means for providing corrected output signals.
Claim 2
Dependent Claim
354 words
A communications system comprising, a plurality of signal repeaters having a first signal repeater receptive of a transmitted signal, a sequence of repeaters receptive of an output signal from a previous repeater and a last repeater, said received signal corresponding to a sequence of information code blocks and at least one checking code block, each information code block being an n-bit binary coded word corresponding to a redundantly encoded piece of information selected from a subset of a set of all n-bit binary code words, and said checking code block being an n-bit binary code word selected from a subset of n-bit binary code words not including said subset of information code blocks, said last repeater comprising first detection means receptive of said signal to develop output signals corresponding to a binary one signal, binary zero signal or an ambiguous signal ambiguous as to logic content thereof, first memory means receptive of said first detector output signals for storing said first detector output signals therein, circuit means receptive of said first detector output signal corresponding to said ambiguous signal levels to store said first detector output signal and develop a first control signal in response thereto, a transformation circuit receptive of said first control signal and said first detector output signals stored in said first memory means for transforming under control of said first control signal an information code block having an ambiguous signal level into a transformed code block selected from a subset of n-bit binary code words not including information code blocks, second detection means receptive of said first detection means output signals from said code transformation circuit for detecting transformed code blocks and developing a second control signal in response thereto, second storage means receptive of said first detectioN means output signals from said code transformation circuit for storing said first detection means output signals therein, an error detecting and correcting circuit connected to said second storage means and receptive of said second control signal for replacing said transformed code block with a correct information code block, and output means connected to said second storage means for providing corrected output signals.
Claim 3
Dependent Claim
95 words
In a communications system according to claim 1 wherein said first detection means comprises a threshold detector having a first and second threshold, said first threshold being greater than said second threshold, for developing said output signal corresponding to a binary one when said received signal level exceeds said first threshold, for developing said output signal corresponding to a binary zero when said received signal level is less than said second threshold, and for developing said output signal corresponding to said ambiguous signal when said received signal level is between said first and second threshold.
Claim 4
Dependent Claim
325 words
A communications system comprising a plurality of signal repeaters having a first signal repeater receptive of a transmitted signal, a sequence of repeaters receptive of an output signal from a previous repeater and a last repeater, said received signal being a sequence of bipolar digital characters having a positive polarity, a negative polarity and a zero level, said received signal being representative of Markov type information such that a first non-zero signal level digital character following a digital character having a positive polarity has a negative polarity, said last signal repeater comprising, first detection means receptive of said received signal for developing output signals corresponding to a positive and negative signal polarity and a zero signal level, second detection means receptive of said received signal for developing a control signal corresponding to an ambiguous signal ambiguous as to logic content thereof, a first and second mode memory for storing said output signals developed by said first detection means, circuit means connected to said first and second detection means and said first and second mode memory for developing an output signal under control of said control signal corresponding to said output signal developed by said first detection means during an absence of said control signal and corresponding to two successive signals representative of said received signal having two successive digital characters each having positive polarity when said control signal is applied to said circuit means memory means receptive of said output signal of said circuit means for storing said output signal therein a mode detecting and correcting circuit receptive of said output signal of said circuit means and connected to said memory means for detecting said two successive output signals representative of two successive digital characters each having positive polarity for correcting said output signal of said circuit means stored in said memory means according to transition rules of said Markov type information, and output means connected to said memory means for providing corrected output signals.
Claim 5
Dependent Claim
325 words
A communications system comprising a plurality of signal repeaters having a first signal repeater receptive of a transmitted signal, a sequence of repeaters receptive of an output signal from a previous repeater and a last repeater, said received signal being a sequence of bipolar digital characters having a positive polarity, a negative polarity and a zero level, said received signal being representative of Markov type information such that a first non-zero signal level digital character following a digital character having a positive polarity has a negative polarity, said last signal repeater comprising, first detection means receptive of said received signal for developing output signals corresponding to a positive and negative signal polarity and a zero signal level, second detection means receptive of said received signal for developing a control signal corresponding to an ambiguous signal ambiguous as to logic content thereof, a first and second mode memory for storing said output signals developed by said first detection means, circuit means connected to said first and second detection means and said first and second mode memory for developing an output signal under control of said control signal corresponding to said output signal developed by said first detection means during an absence of said control signal and corresponding to two successive signals representative of said received signal having two successive digital characters each having positive polarity when said control signal is applied to said circuit means memory means receptive of said output signal of said circuit means for storing said output signal therein a mode detecting and correcting circuit receptive of said output signal of said circuit means and connected to said memory means for detecting said two successive output signals representative of two successive digital characters each having positive polarity for correcting said output signal of said circuit means stored in said memory means according to transition rules of said Markov type information, and output means connected to said memory means for providing corrected output signals.
Claim 6
Dependent Claim
166 words
In a communication system according to claim 3 wherein said first detection means comprises, a threshold detector having a first and second threshold, said first threshold being greater than said second threshold for developing said output signal corresponding to a positive polarity when said received signal level exceeds said first threshold, for developing said output signal corresponding to a negative polarity when said received signal level is less than said second threshold, and for developing no output signal when said received signal level is between said first and second threshold, and wherein said second detection means comprises, a threshold detector having a first, second, third and fourth threshold, said first threshold being greater than said second threshold, said second threshold being greater than said third threshold, and said third threshold being greater than said fourth threshold, for developing said control signal when said received signal level is between said first and second threshold or when said received signal level is between said third and fourth threshold.
References Cited (Backward Citations)
US3449716A
Cited
US3396369A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-18 | 1978-05-20 | 1978-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-18 | 1982-05-20 | 1982-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-18 | 1986-05-20 | 1986-11-19 | $7700.00 | Window Closed / Lapsed |