Phase detector circuitry

Claim 2

A phase detector operative in response to first and second binary signals occurring at a known frequency and recurring in discrete time intervals, comprising means for producing one discrete output when said first and second signals are of similar sense and another discrete output when said first and second signals are of a different sense, a source of pulses, counting means operative to continuously count said pulses and register indications in ascending order or descending order under control of said one or said other discrete output, respectively, and means for synchronizing said registration with one of said signals.

Claim 3

A phase detector as defined in claim 1, wherein the first-mentioned means is an exclusive OR gate having first and second inputs supplied by said recurring binary signals.

Claim 4

A phase detector as defined in claim 1, wherein said first and second signals recur in discrete time intervals only, and said counting means is reset to zero between said time intervals.

Claim 5

A phase detector as defined in claim 3, including means for advancing or retarding the phase of said first signal in accordance with the most significant digit stored in said counting means at the end of each said discrete time interval.

Claim 6

A phase detector as defined in claim 4, wherein said first signal is supplied by a binary adder operating in response to continuously applied pulses having a repetition rate exceeding that of said first and second signals, and means for modifying the input to said adder in accordance with the most significant digit stored in said counting means.

Claim 7

Phase detector circuitry operative in response to binary signals of known repetition rate recurring in discrete time intervals, comprising a binary adder operative to cyclically add in response to pulses occurring at a rate greater than said known repetition rate with a cycle of operation equal to the period of said known repetition rate, means for extracting a binary reference output from said adder having the waveform and repetition rate of said binary signals, a logic OR gate receiving said binary signals and said reference output as inputs thereto, a reversible binary counter, means supplying counting pulses to said counter at a rate in excess of said known repetition rate, means for controlling the direction of count in said counter in accordance with the output of said OR gate, means for resetting said counter to zero after each said discrete time interval, and means for adding a quantity to said binary adder after each said discrete time interval determined by the number registered in said counter.

Claim 8

Phase detector circuitry operative in response to binary signals of known repetition rate recurring in discrete time intervals, comprising a binary adder operative to cyclically add in response to pulses occurring at a rate greater than said known repetition rate with a cycle of operation equal to the period of said known repetition rate, means for extracting a binary reference output from said adder having the waveform and repetition rate of said binary signals, a logic OR gate receiving said binary signals and said reference output as inputs thereto, a reversible binary counter, means supplying counting pulses to said counter at a rate in excess of said known repetition rate, means for controlling the direction of count in said counter in accordance with the output of said OR gate, means for resetting said counter to zero after each said discrete time interval, and means for adding a quantity to said binary adder after each said discrete time interval determined by the number registered in said counter.

Claim 9

Phase detector circuitry as defined in claim 6, wherein the counting pulses are supplied to said counter during said discrete intervals.