High speed programmable counter

Claim 2

A high speed frequency divider responsive to a source of input signals for producing an output signal for every kth input signal, where k is a selectively defined integer, comprising: a first counter for counting when enabled said input signals; a second counter of modulo-n for counting when enabled said input signals and producing the output signal when n signals have been counted; means responsive to a count value of k-n in the first counter for enabling the second counter and disabling the first counter; means responsive to a count value less than n in the second counter for modifying the count value in the first counter; and means responsive to the output signal for enabling the first counter and disabling the second counter.

Claim 3

The invention as claimed in claim 1 wherein the count value in the first counter is modified to a value determined by a selected value of k; and further including means for changing said second counter to modulo-(n-1) when the value of k is even.

Claim 4

The invention as claimed in claim 2 wherein the second counter is a shift register counter and said modulo changing means disables the last stage of the shift register.

Claim 5

A high speed programmable counter comprising the combination of a source of input signals to be counted; a first counter for counting, when enabled, said input signals and producing an output signal when j signals have been counted, where j is a selectable integer within the count range of the first counter; a second counter for counting, when enabled, said input signals, producing first output signals when k-n signals have been counted, and producing a second output signal when k signals have been counted, where k and n are predetermined integers; means responsive to the first counter for enabling the second counter when the value in the first counter is j-k; means responsive to the second counter for disabling the first counter when the second counter is enabled; means responsive to the first output signal of the second counter for modifying the count value in the first counter; means responsive to the second counter for enabling the first counter and disabling the second counter when the count value of the second counter is k.

Claim 6

A high speed programmable counter comprising the combination of a source of input signals to be counted; a first counter for counting, when enabled, said input signals and producing an output signal when j signals have been counted, where j is a selectable integer within the count range of the first counter; a second counter for counting, when enabled, said input signals, producing first output signals when k-n signals have been counted, and producing a second output signal when k signals have been counted, where k and n are predetermined integers; means responsive to the first counter for enabling the second counter when the value in the first counter is j-k; means responsive to the second counter for disabling the first counter when the second counter is enabled; means responsive to the first output signal of the second counter for modifying the count value in the first counter; means responsive to the second counter for enabling the first counter and disabling the second counter when the count value of the second counter is k.

Claim 7

The combination comprising: a plurality of counter stage means cascaded to form a radix counter, said counter having an input; a plurality of logic gate means coupled to the counter stage means for setting a selected value into the radix counter; a plurality of shift register means coupled to form a shift register, said shift register having a shift input and an advance input; a source of signals to be counted; means for coupling the signal source to the input of the radix counter and to the advance input of the shift register; means responsive to the value in the radix counter for applying a first class of signal to the shift input when the value in the radix counter is a first value and for applying a second class of signal to the shift input when the value in the radix counter is a second value; means responsive to the shift register for disabling the radix counter when any shift register means contains a first class of signal; and means responsive to a first class of signal in a certain shift register means for enabling the plurality of logic gate means.

Claim 8

The combination comprising: a plurality of counter stage means cascaded to form a radix counter, said counter having an input; a plurality of logic gate means coupled to the counter stage means for setting a selected value into the radix counter; a plurality of shift register means coupled to form a shift register, said shift register having a shift input and an advance input; a source of signals to be counted; means for coupling the signal source to the input of the radix counter and to the advance input of the shift register; means responsive to the value in the radix counter for applying a first class of signal to the shift input when the value in the radix counter is a first value and for applying a second class of signal to the shift input when the value in the radix counter is a second value; means responsive to the shift register for disabling the radix counter when any shift register means contains a first class of signal; and means responsive to a first class of signal in a certain shift register means for enabling the plurality of logic gate means.

Claim 9

The invention as claimed in claim 5 including means for holding a second class of signal in the last shift register means when an even value is set into the radix counter.