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US3846693A
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US
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Selectively switched, malfunction-responsive three phase and parallel logic box for plural static inverters
Assignee: AVIONIC INSTR Inc
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Filing: 1973-10-16
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Granted: 1974-11-05
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Expires: 1993-10-16
Abstract
Abstract Circuitry for operating static inverters which individually are capable of developing a regulated a.c. output at a controlled frequency rate from a d.c. input. The circuitry derives its d.c. input from one or more of the static inverters for developing synchronizing signals to operate the static inverters so as to enable them to develop three phase a.c. and enables the inverters to be connected in either wye or delta fashion. By means of a single phase/three phase switch a second mode of operation can be obtained for operating the static inverters in a single phase parallel manner. The logic box operation is controlled by a master oscillator which is continuously monitored to ascertain its operation. During normal operation of the master oscillator, the local oscillators of the static inverters connected to the logic box are disabled. In the event of a failure in the master oscillator the local oscillators of the static inverters are automatically enabled to permit continuous operation of the static inverters. The logic box, when combined with three static inverters provides means for driving three phase equipment through the use of single phase power sources (i.e., static inverters) or alternatively, provides an increase in the power capability of the static inverter equipment when operated in single phase parallel fashion.
Inventors
- 👤 A Compoly
- 👤 A Temple
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:30
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/539
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
182 words
A logic control circuit for synchronizing a plurality of static inverters each comprising a local oscillator, a local bistable frequency divider coupled to the local oscillator and an output circuit coupled to the frequency divider for producing a regulated a.c. output at a regulated frequency, said logic control circuit comprising: a master oscillator; multiphase synchronizing means having an input for generating a plurality of phase synchronizing signals at each of its outputs which signals are at equidistant electrical phase intervals, said outputs each being coupled to a respective one of the local bistable frequency dividers of said static inverters for driving the local bistable frequency dividers; sensing means coupled to said master oscillator for sensing the operating condition of said master oscillator to generate a disabling signal only when said master oscillator is opErating properly, which disabling signal is coupled incommon to each of the local oscillators of said static inverters to disable said local oscillators, said disabling signal being terminated upon the malfunctioning of the master oscillator to permit each static inverter to operate under control of its respective local oscillator.
Claim 2
Dependent Claim
182 words
A logic control circuit for synchronizing a plurality of static inverters each comprising a local oscillator, a local bistable frequency divider coupled to the local oscillator and an output circuit coupled to the frequency divider for producing a regulated a.c. output at a regulated frequency, said logic control circuit comprising: a master oscillator; multiphase synchronizing means having an input for generating a plurality of phase synchronizing signals at each of its outputs which signals are at equidistant electrical phase intervals, said outputs each being coupled to a respective one of the local bistable frequency dividers of said static inverters for driving the local bistable frequency dividers; sensing means coupled to said master oscillator for sensing the operating condition of said master oscillator to generate a disabling signal only when said master oscillator is opErating properly, which disabling signal is coupled incommon to each of the local oscillators of said static inverters to disable said local oscillators, said disabling signal being terminated upon the malfunctioning of the master oscillator to permit each static inverter to operate under control of its respective local oscillator.
Claim 3
Dependent Claim
58 words
The logic control circuit of claim 1 further comprising a reference control means coupled to said multiphase synchronizing means; said reference control means being coupled to the frequency dividers of each static inverter to cause all of said frequency dividers to be driven to the same operating state at the beginning of each cycle of the multiphase outputs.
Claim 4
Dependent Claim
24 words
The logic control circuit of claim 1 wherein the local oscillators and the master oscillator are all adapted to operate at the same frequency.
Claim 5
Dependent Claim
47 words
The logic control circuit of claim 1 wherein said synchronizing means further comprises: a control frequency divider coupled to said master oscillator; ring counter means coupled to said control frequency divider; logical gating means coupled to said ring counter means for generating said plurality of synchronizing signals.
Claim 6
Dependent Claim
64 words
The logic control circuit of claim 4 further comprising single phase/multiphase switch means coupled between said logical gating means and said static inverters for generating multiphase signals when in a multiphase operating mode and for generating signals in time synchronism when in the single phase operating mode to respectively operate the static inverter to provide output power for either multiphase or single phase equipment.
Claim 7
Dependent Claim
37 words
The logic control circuit of claim 4 further comprising second logical gating means coupled to said ring counter for generating reference control signals applied to each of the static inverter frequency dividers to control their operating states.
Claim 8
Dependent Claim
59 words
The logic control circuit of claim 6 further comprising second switch means coupled between said second logical gating means and said static inverters for providing multiphase reference signals when said second switch means is in the multiphase operating mode and for providing reference signals in phase synchronism when said second switch means is in the single phase operating mode.
Claim 9
Dependent Claim
37 words
The logic control circuit of claim 1 wherein said synchronizing means generates three output signals each being 120 degrees out of phase with one another to enable the static inverters coupled thereto to power three phase equipment.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-04 | 1978-05-06 | 1978-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-04 | 1982-05-06 | 1982-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-04 | 1986-05-06 | 1986-11-05 | $7700.00 | Window Closed / Lapsed |