Semiconductor fabrication method for accommodating redundancy

Abstract

Abstract 1. AN INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE FABRICATION METHOD FOR UTILIZING SEMICONDUCTOR SUBSTRATES THAT POTENTIALLY EMBODY DEFECTIVE ACTIVE AND PASSIVE DEVICES AND ISOLATION DEFECTS, SAID SUBSTRATE INCLUDING A PLURALITY OF TRANSITOR DEVICES ON OVERLYING INSULATING LAYER, AND CONTACT OPENINGS THROUGH THE LAYER EXPOSING REGIONS DEFINED BY A PN JUNCTION, THE METHOD COMPRISING DEPOSITING A BLANKET LAYER OF ANODIZABLE METAL SELECTED FROM THE GROUP CONSISTING OF NIOBIUM, ZIRCONIUM, TUNGSTEN, TANTALUM, AND ALUMINUM, OVER SAID INSULATING LAYER, FORMING SAID LAYER OF METAL INTO DISCRETE AREAS OVER SAID CONTACT OPENINGS, AND AREAS OF THE INSULATING LAYER, IMMERSING AT LEAST THE SURFACE OF THE SUBSTRATE EMBODYING THE INSULATING LAYER AND METAL LAYER TO AN ELECTROLYTE SOLUTION, IMPRESSING A VOLTAGE ACROSS THE SEMICONDUCTOR SUBSTRATE AND SAID SOLUTION TO MAKE THE SUBSTRATE AN ANODE, SAID VOLTAGE APPLIED TO BACK-BIAS THE PN JUNCTION IN SAID SUBSTRATE IN ELECTRICAL CONTACT WITH SAID METAL AREAS, REMOVING THE BODY FROM THE ELECTROLYTE SOLUTION, REMOVING THE UN-ANODIZED METAL LAYER AREAS, AND FORMING AN INTERCONNECTION METALLURGY PATTERN ON THE SURFACE OF SAID SUBSTRATE OVER ANY REMAINING ANODIZED METAL AREAS, SAID ANODIZED AREAS PREVENTING ELECTRICAL CONTACT FROM BEING FORMED BETWEEN SAID INTERCONNECTION METALLURGY AND THE DEFECTIVE DEVICES AND STRUCTURE IN SAID SUBSTRATE.

Inventors

• 👤 B Duncan
• 👤 D Seto

Bibliographic Details