Patent US3846194A successfully refreshed from Google Patents.
← Back to Patent Explorer
US3846194A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for producing lightly doped p and n-type regions of silicon on an insulating substrate

Assignee: Inselek Inc
•
Filing: 1973-01-05
•
Granted: 1974-11-05
•
Expires: 1993-01-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract 1. A METHOD OF PRODUCING LIGHTLY DOPED P AND NTYPE REGIONS OF SILICON ON AND INSULATING SUBSTRATE COMPRISING FORMING A LAYER OF FIRST TYPE SILICON ON AN INSULATING SUBSTRATE, MASKING A PORTION OF THE SURFACE OF SAID LAYER, FORMING A LAYER OF SECOND TYPE SILICON CONTAINING A CONTROLLED AMOUNT OF COUNTERDOPANT ON AT LEAST THE UNMASKED PORTIONS OF SAID LAYER OF FIRST TYPE SILICON, AND HEATING THE SILICON LAYERS TO A TEMPERATURE AND FOR A TIME SUFFICIENT TO DRIVE A PORTION OF THE COUNTERDOPANT INTO THE UNMASKED REGION OF THE LAYER OF FIRST TYPE SILICON WHEREBY A WAFER IS PRODUCED WHICH HAS LIGHTLY DOPED REGIONS OF P CONDUCTIVITY AND N CONDUCTIVITY AND IT CAN BE USED TO MAKE COMPLEMENTARY TYPES OF PMOS AND NMOS TRANSISTORS.

Inventors

  • 👤 D Dumin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 16:47
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10D86/00; H10D86/01; H10D86/03; H10P14/27; H10P14/271; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/018; Y10S148/026; Y10S148/053; Y10S148/10; Y10S148/122; Y10S148/15; Y10S438/00; Y10S438/969

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 124 words
A METHOD OF PRODUCING LIGHTLY DOPED P AND NTYPE REGIONS OF SILICON ON AND INSULATING SUBSTRATE COMPRISING FORMING A LAYER OF FIRST TYPE SILICON ON AN INSULATING SUBSTRATE, MASKING A PORTION OF THE SURFACE OF SAID LAYER, FORMING A LAYER OF SECOND TYPE SILICON CONTAINING A CONTROLLED AMOUNT OF COUNTERDOPANT ON AT LEAST THE UNMASKED PORTIONS OF SAID LAYER OF FIRST TYPE SILICON, AND HEATING THE SILICON LAYERS TO A TEMPERATURE AND FOR A TIME SUFFICIENT TO DRIVE A PORTION OF THE COUNTERDOPANT INTO THE UNMASKED REGION OF THE LAYER OF FIRST TYPE SILICON WHEREBY A WAFER IS PRODUCED WHICH HAS LIGHTLY DOPED REGIONS OF P CONDUCTIVITY AND N CONDUCTIVITY AND IT CAN BE USED TO MAKE COMPLEMENTARY TYPES OF PMOS AND NMOS TRANSISTORS.
Claim 2
Independent Claim 124 words
A METHOD OF PRODUCING LIGHTLY DOPED P AND NTYPE REGIONS OF SILICON ON AND INSULATING SUBSTRATE COMPRISING FORMING A LAYER OF FIRST TYPE SILICON ON AN INSULATING SUBSTRATE, MASKING A PORTION OF THE SURFACE OF SAID LAYER, FORMING A LAYER OF SECOND TYPE SILICON CONTAINING A CONTROLLED AMOUNT OF COUNTERDOPANT ON AT LEAST THE UNMASKED PORTIONS OF SAID LAYER OF FIRST TYPE SILICON, AND HEATING THE SILICON LAYERS TO A TEMPERATURE AND FOR A TIME SUFFICIENT TO DRIVE A PORTION OF THE COUNTERDOPANT INTO THE UNMASKED REGION OF THE LAYER OF FIRST TYPE SILICON WHEREBY A WAFER IS PRODUCED WHICH HAS LIGHTLY DOPED REGIONS OF P CONDUCTIVITY AND N CONDUCTIVITY AND IT CAN BE USED TO MAKE COMPLEMENTARY TYPES OF PMOS AND NMOS TRANSISTORS.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-11-04 1978-05-06 1978-11-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-11-04 1982-05-06 1982-11-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-11-04 1986-05-06 1986-11-05 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag