Abstract An arrangement for biasing the substrate of an integrated circuit comprises n insulated gate field effect transistors integrated in the substrate and each having a source region, a drain region, and a gate connected to the drain region. The source regions of the n transistors are formed by n zones of opposite type of conductivity to the substrate, and the drain regions of the first to n-1th transistors are formed by the second to nth zones, respectively. The drain region of the nth transistors is formed by an n1th zone of the said opposite type of conductivity, and the second to n+1th zones are capacitively coupled respectively with n electrodes. The arrangement also comprises a signal generator having n outputs which provides at each output a periodic signal which is displaced in time with respect to the periodic signals provided at the other outputs. Each of the n electrodes is connected to one of the m outputs of the signal generator, and the m outputs are connected to respective electrodes in each group of m consecutive electrodes formed from the n electrodes.
In combination: an integrated circuit having a substrate made of semiconductor material of one type of conductivity in which there are integrated n insulated gate field effect transistors each having a source region, a drain region, and a gate connected to the said drain region, the source regions of the said n field effect transistors being formed respectively by n zones of semiconductor material of opposite type of conductivity to the said substrate, the drain regions of the first to n-1th field effect transistors being formed by the second to nth zones respectively, and the drain region of the nth field effect transistor being formed by an n+1th zone of semiconductor material of the said opposite type of conductivity, the second to n+1th zones being capacitively coupled respectively with n electrodes; and signal-generation circuitry having m outputs and operative to provide at each output a periodic signal which is displaced in time with respect to the periodic signals provided at the other outputs; each of the said n electrodes being connected to one of the said m outputs of the signal-generation circuitry, the said m outputs being connected to respective electrodes in each group of m consecutive electrodes formed from the n electrodes.
Claim 2
Dependent Claim
203 words
In combination: an integrated circuit having a substrate made of semiconductor material of one type of conductivity in which there are integrated n insulated gate field effect transistors each having a source region, a drain region, and a gate connected to the said drain region, the source regions of the said n field effect transistors being formed respectively by n zones of semiconductor material of opposite type of conductivity to the said substrate, the drain regions of the first to n-1th field effect transistors being formed by the second to nth zones respectively, and the drain region of the nth field effect transistor being formed by an n+1th zone of semiconductor material of the said opposite type of conductivity, the second to n+1th zones being capacitively coupled respectively with n electrodes; and signal-generation circuitry having m outputs and operative to provide at each output a periodic signal which is displaced in time with respect to the periodic signals provided at the other outputs; each of the said n electrodes being connected to one of the said m outputs of the signal-generation circuitry, the said m outputs being connected to respective electrodes in each group of m consecutive electrodes formed from the n electrodes.
Claim 3
Dependent Claim
116 words
A combination according to claim 1, comprising an n + 1th insulated gate field effect transistor integrated in the substrate and having a source region, a drain region, and a gate, one of the said regions being formed by the n + 1th zone of semiconductor material and the other region being formed by an n + 2th zone of the semiconductor material of the said opposite type of conductivity, and the said substrate also having integrated therein a highly doped zone of the said one type of conductivity, the gate of the n + 1th field effect transistor being galvanically connected to the said n + 2th zone and to the said highly doped zone.