Time delay controller circuit for reducing time jitter between signal groups

Claim 2

A time delay controller circuit for reducing time jitter between successive signal groups of the type wherein each group includes a synchronization pulse and a reference frequency pulse, said controller circuit comprising: time delay means for imposing a time delay on signals processed therethrough as a function of a control signal applied thereto; means for producing a first signal indicative of the time between the synchronization pulse of the input signal group to said time delay means, and the synchronization pulse of the output signal group from said time delay means; means for producing a second signal indicative of the phase difference between the reference frequency pulse of the input signal group to said time delay means and the reference frequency pulse of the output signal group from said time delay means; and means for combining said first and second signals to form said control signal; means for providing a logic signal when said control signal is less than a preselected value; and means responsive to said logic signal, for coupling the output of said time delay device to an output circuit only during time periods in which said control signal is less than said preselected value; whereby the time delay imposed on each signal group within said time delay means is controlled so as to reduce the time jitter between the signal groups.

Claim 3

The controller circuit of claim 1 further comprising means for receiving a third signal indicative of a dynamic time jitter function; and means for combining said third signal with said first and second signals to form said control signal.

Claim 4

The controller circuit of claim 2 wherein said time delay means comprises: first delay means for time delaying signals processed therethrough in accordance with a first function of the frequency of the signals; second delay means series coupled to said first delay means, for time delaying signals processed therethrough in accordance with a second function of the frequency of the signals with said second function being related to said first function such that signals at all frequencies are delayed substantially the same amount in transit through the combination of said first and second delay means; and a first frequency translation means for frequency translating the signals applied to at least one of said delay means as a function of the control signal; whereby the transit time through said time delay means is substantially the same for all frequencies and the magnitude of the transit time is determined by the value of the control signal.

Claim 5

The controller circuit of claim 1 wherein said time delay means comprises: first delay means for time delaying signals processed therethrough in accordance with a first function of the frequency of the signals; second delay means series coupled to said first delay means, for time delaying signals processed therethrough in accordance with a second function of the frequency of the signals with said second function being related to said first function such that signals at all frequencies are delayed substantially the same amount in transit through the combination of said first and second delay means; and a first frequency translation means for frequenCy translating the signals applied to at least one of said delay means as a function of the control signal; whereby the transit time through said time delay means is substantially the same for all frequencies and the magnitude of the transit time is determined by the value of the control signal.

Claim 6

A time delay controller circuit for reducing time jitter between successive signal groups of the type wherein each group includes a synchronization pulse and a reference frequency pulse, said controller circuit comprising: time delay means for imposing a time delay on signals processed therethrough as a function of a control signal applied thereto; means for producing a first signal indicative of the time between the synchronization pulse of the input signal group to said time delay means, and the synchronization pulse of the output signal group from said time delay means; means for producing a second signal indicative of the phase difference between the reference frequency pulse of the input signal group to said time delay means and the reference frequency pulse of the output signal group from said time delay means; means for receiving a third signal indicative of a dynamic time jitter function; and means for combining said first, second and third signals to form said control signal; whereby the time delay imposed on each signal group within said time delay means is controlled so as to reduce the time jitter between the signal groups.

Claim 7

A time delay controller circuit for reducing time jitter between successive signal groups of the type wherein each group includes a synchronization pulse and a reference frequency pulse, said controller circuit comprising: time delay means for imposing a time delay on signals processed therethrough as a function of a control signal applied thereto; means for producing a first signal indicative of the time between the synchronization pulse of the input signal group to said time delay means, and the synchronization pulse of the output signal group from said time delay means; means for producing a second signal indicative of the phase difference between the reference frequency pulse of the input signal group to said time delay means and the reference frequency pulse of the output signal group from said time delay means; means for receiving a third signal indicative of a dynamic time jitter function; and means for combining said first, second and third signals to form said control signal; whereby the time delay imposed on each signal group within said time delay means is controlled so as to reduce the time jitter between the signal groups.

Claim 8

A time delay controller circuit for reducing time jitter between successive signal groups of the type wherein each group includes a synchronization pulse and a reference frequency pulse, said controller circuit comprising: time delay means for imposing a time delay on signals processed therethrough as a function of a control signal applied thereto; said delay means including first delay means for time delaying signals processed therethrough in accordance with a first function of the frequency of the signals, second delay means series coupled to said first delay means, for time delaying signals processed therethrough in accordance with a second function of the frequency of the signals with said second function being related to said first function such that signals at all frequencies are delayed substantially the same amount in transit through the combination of said first and second delay means, and a first frequency translation means for frequency translating the signals applied to at least one of said delay means as a function of the control signal, whereby the transit time through said time delay means is substantially the same for all frequencies and the magnitude of the transit time is determined by the value of the control signal; means for producing a first signal indicative of the time between the synchronization pulse of the input signal group to said time delay means, and the synchronization pulse of the output signal group from said time delay means; means for producing a second signal indicative of the phase difference between the reference frequency pulse of the input signal group to said time delay means and the reference frequency pulse of the output signal group from said time delay means; and means for combining said first and second signals to form said control signal; whereby the time delay imposed on each signal group within said time delay means is controlled so as to reduce the time jitter between the signal groups.

Claim 9

A time delay controller circuit for reducing time jitter between successive signal groups of the type wherein each group includes a synchronization pulse and a reference frequency pulse, said controller circuit comprising: time delay means for imposing a time delay on signals processed therethrough as a function of a control signal applied thereto; said delay means including first delay means for time delaying signals processed therethrough in accordance with a first function of the frequency of the signals, second delay means series coupled to said first delay means, for time delaying signals processed therethrough in accordance with a second function of the frequency of the signals with said second function being related to said first function such that signals at all frequencies are delayed substantially the same amount in transit through the combination of said first and second delay means, and a first frequency translation means for frequency translating the signals applied to at least one of said delay means as a function of the control signal, whereby the transit time through said time delay means is substantially the same for all frequencies and the magnitude of the transit time is determined by the value of the control signal; means for producing a first signal indicative of the time between the synchronization pulse of the input signal group to said time delay means, and the synchronization pulse of the output signal group from said time delay means; means for producing a second signal indicative of the phase difference between the reference frequency pulse of the input signal group to said time delay means and the reference frequency pulse of the output signal group from said time delay means; and means for combining said first and second signals to form said control signal; whereby the time delay imposed on each signal group within said time delay means is controlled so as to reduce the time jitter between the signal groups.

Claim 10

The controller circuit of claim 6 further comprising means for receiving a third signal indicative of a dynamic time jitter function; and means for combining said third signal with said first and second signals to form said control signal.