Patent US3842347A successfully refreshed from Google Patents.
US3842347A
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Rate measurement circuit
Assignee: Varco International Inc
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Filing: 1973-07-03
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Granted: 1974-10-15
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Expires: 1993-07-03
Abstract
Abstract A time/rate converter measures the elapsed time between two events and generates a count proportional to the elapsed time which is stored in a memory. The count is then compared with a reference count and a signal is added to an output counter every time the count is equal to the reference count. Thus, the output counter accumulates an indication of how many equalities occur between the count and the reference count and an accurate indication of rate is achieved.
Inventors
- 👤 W Terbrack
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:38
CPC Classifications
G; G04; G04F; G04F10/00; G04F10/04; G01; G01P; G01P3/00; G01P3/42; G01P3/44; G01P3/48; G01P3/481; G01P3/489; G01P3/64; G01P3/66
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
119 words
A rate measurement circuit comprising: means for measuring each elapsed time interval between successive events and for storing a first count indicative of each elapsed time in a storage memory; time reference means for producing signals for a predetermined duration; first counter means electrically coupled to said time reference means for counting the signals from said time reference means; and comparator means coupled to said storage memory and said first counter means for comparing the first count in said storage memory with the count in said first counter and for providing an output pulse when the first count equals the count in said first counter means, the sum of the output pulses being the rate of the successive events.
Claim 2
Dependent Claim
119 words
A rate measurement circuit comprising: means for measuring each elapsed time interval between successive events and for storing a first count indicative of each elapsed time in a storage memory; time reference means for producing signals for a predetermined duration; first counter means electrically coupled to said time reference means for counting the signals from said time reference means; and comparator means coupled to said storage memory and said first counter means for comparing the first count in said storage memory with the count in said first counter and for providing an output pulse when the first count equals the count in said first counter means, the sum of the output pulses being the rate of the successive events.
Claim 3
Dependent Claim
15 words
The rate measurement circuit as in claim 1 wherein said time reference means is variable.
Claim 4
Dependent Claim
20 words
The rate measurement circuit as in claim 2 wherein the signals produced by said time reference means are clock pulses.
Claim 5
Dependent Claim
187 words
A rate measurement circuit comprising: means for measuring elapsed time between two events and for storing a first count indicative of the elapsed time in a storage memory, said means for measuring elapsed time and for storing a first count indicative of the elapsed time Includes: means for sensing the time between two events, a programmable frequency generator having a selectable output frequency electrically coupled to said sensing means and providing output signals for the elapsed time, and a second counter electrically coupled to said programmable frequency generator for counting the output signals from said programmable frequency generator; time reference means for producing signals for a predetermined duration; first counter means electrically coupled to said time reference means for counting the signals from said time reference means; and comparator means coupled to said storage memory and said first counter means for comparing the first count in said storage memory with the count in said first counter and for providing an output pulse when the first count equals the count in said first counter means, the sum of the output pulses being the rate of the successive events.
Claim 6
Dependent Claim
187 words
A rate measurement circuit comprising: means for measuring elapsed time between two events and for storing a first count indicative of the elapsed time in a storage memory, said means for measuring elapsed time and for storing a first count indicative of the elapsed time Includes: means for sensing the time between two events, a programmable frequency generator having a selectable output frequency electrically coupled to said sensing means and providing output signals for the elapsed time, and a second counter electrically coupled to said programmable frequency generator for counting the output signals from said programmable frequency generator; time reference means for producing signals for a predetermined duration; first counter means electrically coupled to said time reference means for counting the signals from said time reference means; and comparator means coupled to said storage memory and said first counter means for comparing the first count in said storage memory with the count in said first counter and for providing an output pulse when the first count equals the count in said first counter means, the sum of the output pulses being the rate of the successive events.
Claim 7
Dependent Claim
22 words
The rate measurement circuit as in claim 4 wherein a binary coded decimal switch is electrically coupled to said programmable frequency generator.
Claim 8
Dependent Claim
32 words
The rate measurement circuit as in claim 4 further including a crystal oscillator being electrically connected to an input of said programmable frequency generator and an input of said time reference means.
Claim 9
Dependent Claim
41 words
The rate measurement circuit as in claim 4 further including a reset means coupled between said comparator means and said first counter means, each output pulse from said comparator means providing the resetting of said first counter through said reset means.
Claim 10
Dependent Claim
17 words
The rate measurement circuit as in claim 7 wherein said first counter means is a synchronous counter.
References Cited (Backward Citations)
US3537003A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-14 | 1978-04-15 | 1978-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-14 | 1982-04-15 | 1982-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-14 | 1986-04-15 | 1986-10-15 | $7700.00 | Window Closed / Lapsed |