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US3842291A
Expired / Lapsed
US
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Circuit for the suppression of interference pulses
Assignee: Siemens AG
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Filing: 1973-06-13
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Granted: 1974-10-15
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Expires: 1993-06-13
Abstract
Abstract A circuit for the suspension of interference pulses such as those resulting from holes in a machine part which is magnetically coupled to a triggering circuit in which the interference pulses, which have polarities opposite to those of the signal to be detected, are used to ground the trigger circuit output when such pulses are sensed.
Inventors
- 👤 A Maringer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:40
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
145 words
An interference suppression system comprising: a sensing device which periodically produces a first occurring full wave consisting of a positive halfwave portion and a negative halfwave portion; a trigger circuIt coupled to said sensing device and responsive to only the first occuring halfwave portion of said positive and negative halfwave portions of said first occuring full wave; said circuit comprising: a. a first switching transistor responsive only to the halfwave portion of polarity opposite to that of said first occuring halfwave; b. an integrator having an input connected to the output of said first switching transistor; and c. a second switching transistor connected between the output of said integrator and said trigger circuit output to shortcircuit the output of the trigger circuit for the duration of said integrator output thereby suppressing interference pulses that would otherwise be generated as a result of said interference signals.
Claim 2
Dependent Claim
145 words
An interference suppression system comprising: a sensing device which periodically produces a first occurring full wave consisting of a positive halfwave portion and a negative halfwave portion; a trigger circuIt coupled to said sensing device and responsive to only the first occuring halfwave portion of said positive and negative halfwave portions of said first occuring full wave; said circuit comprising: a. a first switching transistor responsive only to the halfwave portion of polarity opposite to that of said first occuring halfwave; b. an integrator having an input connected to the output of said first switching transistor; and c. a second switching transistor connected between the output of said integrator and said trigger circuit output to shortcircuit the output of the trigger circuit for the duration of said integrator output thereby suppressing interference pulses that would otherwise be generated as a result of said interference signals.
Claim 3
Dependent Claim
25 words
The invention according to claim 1 wherein said first switching transistor is coupled through a first amplifier transistor responsive to said one of said halfwaves.
Claim 4
Dependent Claim
30 words
The invention according to claim 2 wherein the trigger circuit includes a trigger transistor and further including a second amplifier transistor between said trigger transistor and the trigger circuit output.
Claim 5
Dependent Claim
23 words
The invention according to claim 3 wherein said integrator comprises an operation amplifier having a capacitor between its output and its inverting input.
Claim 6
Dependent Claim
17 words
The invention according to claim 4 and further including a Zener diode in parallel with said capacitor.
Claim 7
Dependent Claim
76 words
The invention according to claim 5 wherein the output of said first switching transistor is coupled to the input of said integrator through a diode and resistor in parallel whereby said integrator integrates in one direction in response to said first switching transistor responding to said first switching transistor is not responding and said resistance and diode in parallel cause the integration constant in said one direction to be smaller than that for said other direction.
Claim 8
Dependent Claim
50 words
The invention according to claim 6 wherein said integrator output is coupled to the base of said second switching transistor through a pair of diodes in series, the polarity of said diodes being in the cut off direction with respect to the voltage provided by integrating in said one direction.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-14 | 1978-04-15 | 1978-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-14 | 1982-04-15 | 1982-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-14 | 1986-04-15 | 1986-10-15 | $7700.00 | Window Closed / Lapsed |