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US3735154A Expired / Lapsed US ⏱️ 0.0 years remaining

Disabling circuit having a predetermined disabling interval

Assignee: United States Department of the Navy
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Filing: 1971-11-19
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Granted: 1973-05-22
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Expires: 1991-11-19
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Abstract

Abstract A disabling circuit having an integrator-threshold device, a pulse generator such as a monostable multivibrator and a shaper for delivering an output pulse to a load. A feedback path including a semiconductive switch element from the output of the multivibrator to the integrator-threshold device inhibits operation of the integrator for a predetermined time interval determined by the duration of the multivibrator pulse. The monostable multivibrator includes semiconductive circuitry which draws no power in the OFF condition and further includes a FET to insure rapid transition from the ON mode to the OFF mode of operation.

Inventors

  • 👤 G Meeker
  • 👤 A Pertman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 13:08
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K17/041; H03K17/0412; H03K17/04126

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 239 words
A signal disabling circuit coupled between a signal source and a utilization device comprising: an integrator circuit comprising a parallel connected resistor capacitor combination connected to said source; a threshold sensing circuit comprising a zener diode in series with a first transistor connected to said integrator for providing a trigger signal when said integrator circuit reaches a predetermined threshold value, said predetermined voltage determined by the breakdown voltages of said zener diode and said first transistor; a monostable multivibrator coupled to said threshold sensing circuit comprising a second transistor rendered conductive upon receipt of said trigger signal, a third transistor rendered conductive when said second transistor is rendered conductive, a field effect transistor, and a capacitor shunted across said field effect transistor, said capacitor charging when said second transistor and said third transistor are rendered conductive, said capacitor rapidly discharging through said field effect transistor when said second transistor and said third transistor are rendered nonconductive thereby enabling quick retriggering of said multivibrator, said second transistor and said third transistor drawing no power in their OFF mode, and a signal inhibitor circuit including a feedback path and a fourth transistor in parallel with said integrator coupled between the output of said multivibrator and the input of said integrator for precluding the transfer of signals for a predetermined time from said source to said utilization device through said disabling circuit; said utilization device coupled to the output of said multivibrator.
Claim 2
Dependent Claim 239 words
A signal disabling circuit coupled between a signal source and a utilization device comprising: an integrator circuit comprising a parallel connected resistor capacitor combination connected to said source; a threshold sensing circuit comprising a zener diode in series with a first transistor connected to said integrator for providing a trigger signal when said integrator circuit reaches a predetermined threshold value, said predetermined voltage determined by the breakdown voltages of said zener diode and said first transistor; a monostable multivibrator coupled to said threshold sensing circuit comprising a second transistor rendered conductive upon receipt of said trigger signal, a third transistor rendered conductive when said second transistor is rendered conductive, a field effect transistor, and a capacitor shunted across said field effect transistor, said capacitor charging when said second transistor and said third transistor are rendered conductive, said capacitor rapidly discharging through said field effect transistor when said second transistor and said third transistor are rendered nonconductive thereby enabling quick retriggering of said multivibrator, said second transistor and said third transistor drawing no power in their OFF mode, and a signal inhibitor circuit including a feedback path and a fourth transistor in parallel with said integrator coupled between the output of said multivibrator and the input of said integrator for precluding the transfer of signals for a predetermined time from said source to said utilization device through said disabling circuit; said utilization device coupled to the output of said multivibrator.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-05-21 1976-11-20 1977-05-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-05-21 1980-11-20 1981-05-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-05-21 1984-11-20 1985-05-22 $7700.00 Window Closed / Lapsed

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