Circuit for implementing rounding in add/subtract logic networks

Claim 2

An add/subtract circuit for a digital computer comprising: a. n full-adder stages each having first and second operand input terminals, a carry input terminal, a sum output terminal and a carry output terminal; b. means connecting said full-adder stages in tandem with the carry output terminal of a lower order stage connected to the carry input terminal of its adjacent higher order stage; c. means for applying corresponding bits of two n-bit operands individually to the first and second operand input terminals of said n full-adder stages; d. logic means responsive to the bit permutations of the least significant bits of the operands and to a signal determinative of the arithmetic operation being performed, for producing a control signal; and c. means for applying said control signal to the carry input terminal of the lowest order full-adder stage such that the result of said arithmetic operation developed at said sum output terminals approaches a perfectly rounded result.

Claim 3

An add/subtract circuit in which rounding is accomplished simultaneously with the formation of the result, comprising: a. n full-adder stages each having first and second operand input terminals, a carry input terminal, a sum output terminal and a carry oUtput terminal; b. means connecting said full-adder stages in tandem with the carry output terminal of a lower order stage connected to the carry input terminal of its adjacent higher order stage; c. means for applying corresponding bits of two n-bit operands A and B individually to the first and second operand input terminals of said n full-adder stages; d. logic means responsive to the permutations of the least significant bits of the operands (A0 and B0) and to a signal determinative of the arithmetic operation being performed (addition or subtraction) for producing a Carry-In control signal in accordance with the Boolean equation Carry-In A0 + B0 + Subtract; and e. means for applying said Carry-In control signal to the carry input terminal of the lowest order full-adder stage.

Claim 4

An add/subtract circuit in which rounding is accomplished simultaneously with the formation of the result, comprising: a. n full-adder stages each having first and second operand input terminals, a carry input terminal, a sum output terminal and a carry oUtput terminal; b. means connecting said full-adder stages in tandem with the carry output terminal of a lower order stage connected to the carry input terminal of its adjacent higher order stage; c. means for applying corresponding bits of two n-bit operands A and B individually to the first and second operand input terminals of said n full-adder stages; d. logic means responsive to the permutations of the least significant bits of the operands (A0 and B0) and to a signal determinative of the arithmetic operation being performed (addition or subtraction) for producing a Carry-In control signal in accordance with the Boolean equation Carry-In A0 + B0 + Subtract; and e. means for applying said Carry-In control signal to the carry input terminal of the lowest order full-adder stage.

Claim 5

An add/subtract network in which rounding is accomplished simultaneously with the formation of the result, comprising: a. a plurality of groups of n full-adder stages, each stage having first and second operand input terminals, a carry input terminal, a sum output terminal and a carry output terminal; b. means connecting the n full-adder stages of each of said individual groups in tandem with the carry output terminal of a lower order stage in a group connected to the carry input terminal of its adjacent higher order stage in that group; c. means for applying corresponding ordered bits of two n bit operands to the operand input terminals of corresponding stages in said plurality of groups of n full-adder stages; d. logic means responsive to the bit permutations of predetermined bit positions of the operands and to signals determinative of the arithmetic operation being performed by said plurality of groups for producing plural control signals; and e. means for applying said plural control signals individually to the carry input terminal of each of the lowest order full-adder stages of said plurality of groups such that the result of said arithmetic operation developed at said sum output terminals of one of said plurality of groups approaches a perfectly rounded result.

Claim 6

An add/subtract network in which rounding is accomplished simultaneously with the formation of the result, comprising: a. a plurality of groups of n full-adder stages, each stage having first and second operand input terminals, a carry input terminal, a sum output terminal and a carry output terminal; b. means connecting the n full-adder stages of each of said individual groups in tandem with the carry output terminal of a lower order stage in a group connected to the carry input terminal of its adjacent higher order stage in that group; c. means for applying corresponding ordered bits of two n bit operands to the operand input terminals of corresponding stages in said plurality of groups of n full-adder stages; d. logic means responsive to the bit permutations of predetermined bit positions of the operands and to signals determinative of the arithmetic operation being performed by said plurality of groups for producing plural control signals; and e. means for applying said plural control signals individually to the carry input terminal of each of the lowest order full-adder stages of said plurality of groups such that the result of said arithmetic operation developed at said sum output terminals of one of said plurality of groups approaches a perfectly rounded result.

Claim 7

Apparatus as in claim 3 wherein said logic means includes circuits for generating first and second control signals in accordance with the Boolean equations: AC Carry-In AP + A0 + C0 and BD Carry-In SP (BP + B0 + D0), where A0, B0, C0 and D0 are the least significant bits of the operands to be combined and AP, BP and SP are control signals determining whether a particular group of said plurality is to add or subtract the operands applied to its operand input terminals.

Claim 8

Apparatus as in claim 4 and further including: circuitry in said logic means for generating an additional control signal AC/BD Carry-In in accordance with the Boolean equation: AC/BD Carry-In AC0 . BD0 + AP A0 C0 BP B0 D0 + (BD0 + AC0) ((A0 C0 + A0 C0) (B0 D0 + B0 D0) + BP B0 D0 + AP A0 C0) where AC0 and BD0 represent the sum of the lowest order bits of the operands A and C or B and D, respectively.

Claim 9

Apparatus as in claim 5 wherein said means for applying said plural control signals comprises means connecting said first and second control signals to the carry input terminal of the lowest order stages in first and second of said plurality of groups, and said additional control signal to the carry input terminal of the lowest order stage of a third of said plurality of groups when said third group is to add the operand combinations applied as inputs to the operand input terminals.

Claim 10

Apparatus as in claim 4 and further including: circuiTry in said logic means for generating an additional control signal AC/BD Carry-In in accordance with the Boolean equation: AC/BD Carry-In ((B0 + D0) (BP + D0)) (B0 D0 + B0 D0) (A0 C0 + A0 C0) + ((B0 + D0) (BP + D0)) (AP A0 C0) + BD0 . AC0 + (BD0 + AC0) ((A0 C0 + A0 C0) (B0 D0 + B0 D0) + (B0 D0) (BP + D0) + AP A0 C0) where AC0 and BD0 represent the sum of the lowest order bits of the operands A and C or B and D, respectively.

Claim 11

Apparatus as in claim 7 wherein said means for applying said plural control signals comprises means connecting said first and second control signals to the carry input terminal of the lowest order stages in first and second of said plurality of groups and said additional control signal to the carry input terminal of the lowest order stage of a third of said plurality of groups when said third group is to subtract the operand combinations applied as inputs to the operand input terminals.