Rounding numbers expressed in 2{40 s complement notation

Claim 2

Apparatus for rounding 2''s complement numbers in a binary computer to numbers having n less bits comprising: A. an adder for generating the binary sum of two operands; B. rounding means for applying the rounding number 2n 1-1 to said adder as a first operand for a negative number to be rounded; C. rounding means for applying the rounding number 2n 1 to said adder as a first operand for a positive number to be rounded; D. means for applying a 2''s complement binary number to said adder as a second operand.

Claim 3

Apparatus for rounding 2''s complement numbers in a binary computer to numbers having n less bits comprising: A. an adder for generating the binary sum of two operands; B. rounding means for applying the rounding number 2n 1-1 to said adder as a first operand; C. means for applying a 2''s complement binary number to said adder as a second operand; D. correction means for applying a carry-in to said adder in response to a zero in the sign position of said 2''s complement binary number applied to said adder.

Claim 4

Apparatus for rounding 2''s complement numbers in a binary computer to numbers having n less bits comprising: A. an adder for generating the binary sum of two operands; B. rounding means for applying the rounding number 2n 1-1 to said adder as a first operand; C. means for applying a 2''s complement binary number to said adder as a second operand; D. correction means for applying a carry-in to said adder in response to a zero in the sign position of said 2''s complement binary number applied to said adder.

Claim 5

The apparatus of claim 2 further comprising: E. a register for storing said binary number applied as a second operand for said adder; F. operand switching means, included in said means for applying a 2''s complement binary number to said adder, interconnecting said register and said adder; G. register input switching means for selectively gating said 2''s complement binary number to be rounded or said adder output to said register; H. means connecting the output of said adder to said register input switching means.

Claim 6

The apparatus of claim 3 further comprising: I. an accumulator register connected to said register input switching means for providing said 2''s complement binary number to be rounded; J. accumulator switching means interconnecting said adder and said accumulator in such a manner that the contents of said accumulator register are selectively rounded and returned to said accumulator register.

Claim 7

The apparatus of claim 4 further comprising: K. shift switching means, connected between said register for storing said second operand and said operand switching means, for normalizing said operand; L. control means, responsive to said operand register, for directing a rounded operand in said operand register through said shift switching means and said operand switching means back to said operand register, until said operand is normalized.

Claim 8

In a binary computer, having the capability of processing floating point numbers in a binary 2''s complement representation, apparatus for rounding such numbers to a representation having n less bits comprising: A. an adder for generating the binary sum of two operands; B. an accumulator register for storing the output of said adder; C. first and second operand registers for storing operands; D. first and second operand switching means connecting said first and second operand registers, respectively, to said adder; E. an output switch For storing data words in a main memory; F. accumulator input switching means for selectively connecting said adder to said accumulator register and said output switch; G. accumulator output switching means for selectively connecting said accumulator register to said second operand register; H. a rounding constant generator, connected to said first operand switching means, for applying the value 2n 1-1 as the first operand for said adder; I. means for applying a carry-in to said adder in response to a positive sign bit in said second operand register.

Claim 9

In a binary computer, having the capability of processing floating point numbers in a binary 2''s complement representation, apparatus for rounding such numbers to a representation having n less bits comprising: A. an adder for generating the binary sum of two operands; B. an accumulator register for storing the output of said adder; C. first and second operand registers for storing operands; D. first and second operand switching means connecting said first and second operand registers, respectively, to said adder; E. an output switch For storing data words in a main memory; F. accumulator input switching means for selectively connecting said adder to said accumulator register and said output switch; G. accumulator output switching means for selectively connecting said accumulator register to said second operand register; H. a rounding constant generator, connected to said first operand switching means, for applying the value 2n 1-1 as the first operand for said adder; I. means for applying a carry-in to said adder in response to a positive sign bit in said second operand register.