Patent US3840829A successfully refreshed from Google Patents.
US3840829A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated p-channel mos gyrator
Assignee: Individual
•
Filing: 1973-02-02
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Granted: 1974-10-08
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Expires: 1993-02-02
Abstract
Abstract A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180* phase reversal, in a circuit having medium Q composed of all field effect transistors of the same conductivity type. The current source to each gyrator amplifier comprises an amplifier which responds to changes in current, with the amplified signals fed back so as to limit current. The feedback amplifier has a large capacitor connected to bypass high frequency components and thereby stabilize the output. The design makes possible fabrication of circuits with transistors of only one conductivity type, providing economies in manufacture and use.
Inventors
- 👤 J Fletcher
- 👤 E Hochmair
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:39
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/40; H03H11/42
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
185 words
A gyrator circuit comprising a first and a second gyrator amplifier, each comprising a first field effect transistor to amplify signals, the output of each said first and second gyrator amplifier being connected to the input of the other, one of the output signals of one of the amplifiers connected to the input of the other to apply signals phase reversed from the output signals of the one and the other connected to the input of the one to apply signals of the same phase as the output signals of the other, each said gyrator amplifier having connected as the source of current to it a circuit comprising an additional field effect transistor connected source-to-drain to the drain of said field effect transistor of its associated gyrator amplifier, means to sense changes in current to the associated gyrator amplifier, means to amplify said observed changes, and means to return said amplified signals to the gate of said additional transistor so as to limit said changes in current to relatively small changes when the changes in voltage input to the associated gyrator amplifier are relatively large.
Claim 2
Dependent Claim
185 words
A gyrator circuit comprising a first and a second gyrator amplifier, each comprising a first field effect transistor to amplify signals, the output of each said first and second gyrator amplifier being connected to the input of the other, one of the output signals of one of the amplifiers connected to the input of the other to apply signals phase reversed from the output signals of the one and the other connected to the input of the one to apply signals of the same phase as the output signals of the other, each said gyrator amplifier having connected as the source of current to it a circuit comprising an additional field effect transistor connected source-to-drain to the drain of said field effect transistor of its associated gyrator amplifier, means to sense changes in current to the associated gyrator amplifier, means to amplify said observed changes, and means to return said amplified signals to the gate of said additional transistor so as to limit said changes in current to relatively small changes when the changes in voltage input to the associated gyrator amplifier are relatively large.
Claim 3
Dependent Claim
22 words
The circuit as in claim 1 in which all transistors in said circuit are field effect transistors of the same conductivity type.
Claim 4
Dependent Claim
36 words
The circuit as in claim 1 in which at least one of said means to amplify said observed changes is connected to a relatively large impedance effective to stabilize the signals amplified against changes with frequency.
Claim 5
Dependent Claim
86 words
The circuit as in claim 2 in which at least one of said circuits connected as a source of current comprises a resistance element to sense said changes in current with said additional field effect transistor connected between said resistance element and the source-to-drain circuit of the field effect transistor of the associated gyrator amplifier, and also comprises an amplifier with the input connected to the junction of said resistance element and said additional transistor and the output connected to the gate of said additional transistor.
Claim 6
Dependent Claim
87 words
The circuit as in claim 2 in which at least one of said circuits connected as a source of current comprises said additional field effect transistor with the source connected to the source-to-drain circuit of the field effect transistor of the associated gyrator amplifier and a differential amplifier with one input connected to the gate of said additional transistor and the other input connected to the source of said additional transistor, the output of said differential amplifier also being connected to the gate of said additional transistor.
Claim 7
Dependent Claim
35 words
The circuit as in claim 5 in which the input circuit to said differential amplifier contains a source of reference potential to thereby control the nominal level of current through said additional field effect transistor.
Claim 8
Dependent Claim
97 words
The circuit as in claim 4 in which said signals sensed from said resistance element are connected to the gate of one field effect transistor, the output of said one field effect transistor is connected to the gate of a second field effect transistor, and the output of said second field effect transistor is connected across a relatively large capacitor to a source of reference potential and is connected to the gate of a third field effect transistor, and in which said third field effect transistor is connected to the gate of said additional field effect transistor.
Claim 9
Dependent Claim
21 words
The circuit as in claim 7 in which all transistors in said circuit are p-channel metal oxide semiconductor field effect transistors.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-07 | 1978-04-08 | 1978-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-07 | 1982-04-08 | 1982-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-07 | 1986-04-08 | 1986-10-08 | $7700.00 | Window Closed / Lapsed |