Patent US3840753A successfully refreshed from Google Patents.
US3840753A
Expired / Lapsed
US
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Tape read amplifier and logic circuit
Assignee: Texas Instruments Inc
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Filing: 1972-10-02
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Granted: 1974-10-08
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Expires: 1992-10-02
Abstract
Abstract Disclosed is an improved logic gate circuit utilizing a flipflop as a gating element to ineffectuate a noise portion of an input signal. A flip-flop and a gate circuit are responsive to the same input signals, and the flip-flop generates in response thereto a gating input signal to the logic gate to thereby gate out regions of possible noise. The improved logic gate is advantageously utilized in a high speed tape-read amplifier circuit providing both high and low level noise rejection in the NRZ mode.
Inventors
- 👤 J Kuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:03
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017545; H03K3/00; H03K3/01; H03K3/013
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
38 words
In an electronic logic circuit the combination comprising: a logic gate responsive to a plurality of logic input signals and a flip-flop coupled to said gate for generating another input logic signal thereto in response to said plurality.
Claim 2
Dependent Claim
38 words
In an electronic logic circuit the combination comprising: a logic gate responsive to a plurality of logic input signals and a flip-flop coupled to said gate for generating another input logic signal thereto in response to said plurality.
Claim 3
Dependent Claim
16 words
The logic circuit according to claim 1 wherein said flip-flop is responsive only to said plurality.
Claim 4
Dependent Claim
14 words
The logic circuit of claim 2 wherein said logic gate is an AND gate.
Claim 5
Dependent Claim
14 words
The logic circuit of claim 2 wherein said logic gate is a NAND gate.
Claim 6
Dependent Claim
25 words
The logic circuit of claim 2 wherein said flip-flop is a J-K flip-flop which is actuated by the falling edges of said input logic signals.
Claim 7
Dependent Claim
24 words
The logic circuit of claim 3 wherein said plurality consists of two signals which respectively actuate said flip-flop into the set and reset state.
Claim 8
Dependent Claim
35 words
An improved logic element comprising a logic gate responsive to a plurality of input signals and a flip-flop also responsive to said plurality of input signals for generating another input signal to said logic gate.
Claim 9
Dependent Claim
35 words
An improved logic element comprising a logic gate responsive to a plurality of input signals and a flip-flop also responsive to said plurality of input signals for generating another input signal to said logic gate.
Claim 10
Dependent Claim
15 words
The improved logic gate of claim 7 wherein said gate is a logic AND gate.
Claim 11
Dependent Claim
15 words
The improved logic gate of claim 7 wherein said gate is a logic NAND gate.
Claim 12
Dependent Claim
26 words
The improved logic gate of claim 7 wherein said flip-flop is an edge-triggered J-K flip-flop actuated by the falling edges of said plurality of input signals.
Claim 13
Dependent Claim
15 words
The logic element of claim 7 wherein said flip-flop is responsive only to said plurality.
Claim 14
Dependent Claim
65 words
A tape-read amplifier circuit responsive to a plurality of logic input signals for providing a logic output signal representing a logic combination of said input signals, the combination including: a. a logic gate for generating said output signals in response to first, second and third input signals, and b. a flip-flop responsive to said first and second input signals for generating said third input signal.
Claim 15
Dependent Claim
65 words
A tape-read amplifier circuit responsive to a plurality of logic input signals for providing a logic output signal representing a logic combination of said input signals, the combination including: a. a logic gate for generating said output signals in response to first, second and third input signals, and b. a flip-flop responsive to said first and second input signals for generating said third input signal.
Claim 16
Dependent Claim
29 words
The tape read amplifier circuit of claim 12 wherein said flip-flop circuit includes an edge-triggered J-K flip-flop actuated by the falling edges of said first and second input signals.
Claim 17
Dependent Claim
90 words
The tape-read amplifier circuit of claim 13 and further including: a. clipping circuit means responsive to a fourth input signal for selectively providing said second input signal in a first binary state only when said fourth input signal exceeds a preselected threshold level; b. differentiator means responsive to said fourth input signal to provide an analog differentiator signal; and c. a zero detector circuit responsive to said differentiator signal for providing said first input signal in a second binary state when said differentiator signal lies within a preselected magnitude range.
Claim 18
Dependent Claim
23 words
The tape-read amplifier circuit of claim 14 wherein said preselected magnitude range is substantialLy zero and said amplifier circuit comprises an NRZ amplifier.
Claim 19
Dependent Claim
26 words
The tape-read amplifier circuit of claim 15 wherein said differentiator means comprises an operational amplifier having an input capacitively coupled to receive said fourth input signal.
Claim 20
Dependent Claim
55 words
The tape-read amplifier circuit of claim 16 wherein said zero detector circuit comprises: a. a reference amplifier responsive to a reference voltage signal for providing a reference voltage range; and b. a comparator for comparing said differentiator signal with said reference voltage range and for generating said first input signal in said second binary state.
Claim 21
Dependent Claim
51 words
The tape-read amplifier circuit of claim 17 wherein: a. said reference amplifier has another input adapted to receive a bias voltage and has an output coupled to said comparator; and b. said comparator has an input coupled to said differentiator means and has an output to provide said first input signal.
Claim 22
Dependent Claim
59 words
The tape-read amplifier circuit of claim 18 wherein said clipping circuit means comprises: a. a second reference amplifier responsive to second reference voltage signal for providing a second reference voltage range; and b. a second comparator for comparing said fourth input signal with said second reference voltage range and generating said second input signal in said first binary state.
Claim 23
Dependent Claim
21 words
The tape-read amplifier circuit of claim 19 wherein the output terminal of said second comparator is capacitively coupled to circuit ground.
Claim 24
Dependent Claim
23 words
The tape-read amplifier circuit of claim 20 and further including an amplifier circuit for providing said fourth input signal in an amplified condition.
Claim 25
Dependent Claim
34 words
The tape-read amplifier circuit of claim 12, wherein said logic gate circuit includes an AND gate to which said first, second, and third input signals are to be applied for generating said output signal.
Claim 26
Dependent Claim
34 words
The tape-read amplifier circuit of claim 12, wherein said logic gate circuit includes a NAND gate to which said first, second, and third input signals are to be applied for generating said output signal.
Claim 27
Dependent Claim
108 words
The tape-read amplifier circuit comprising: a. clipping circuit means responsive to a first input signal for selectively providing a second input signal in a first binary state only when said first input signal exceeds a preselected threshold level; b. differentiator means responsive to said first input signal to provide an analog differentiator signal; c. a zero detector circuit responsive to said differentiator signal for providing a third input signal in a second binary state when said differentiator signal lies within a preselected magnitude range; and d. logic means responsive to said second and said third input signals for indicating the presence of data on said first input signal.
Claim 28
Dependent Claim
108 words
The tape-read amplifier circuit comprising: a. clipping circuit means responsive to a first input signal for selectively providing a second input signal in a first binary state only when said first input signal exceeds a preselected threshold level; b. differentiator means responsive to said first input signal to provide an analog differentiator signal; c. a zero detector circuit responsive to said differentiator signal for providing a third input signal in a second binary state when said differentiator signal lies within a preselected magnitude range; and d. logic means responsive to said second and said third input signals for indicating the presence of data on said first input signal.
Claim 29
Dependent Claim
43 words
The tape-read amplifier circuit according to claim 24 wherein said logic means includes: a. a flip-flop responsive to said second and third input signals for generating a fourth input signal; and b. a gate responsive to said second, third and fourth input signals.
Claim 30
Dependent Claim
24 words
The tape-read amplifier circuit according to claim 25 wherein said preselected magnitude range is substantially zero, and said amplifier circuit comprises an NRZ amplifier.
Claim 31
Dependent Claim
26 words
The tape amplifier according to claim 26 wherein said differentiator means comprises an operational amplifier having an input capacitively coupled to receive said first input signal.
Claim 32
Dependent Claim
58 words
The tape amplifier circuit according to claim 27 wherein said zero detector circuit comprises: a. a reference amplifier responsive to a reference voltage signal for providing a first reference voltage range; and b. a comparator for comparing said differentiator signal with said first reference voltage range and for generating said first input signal in said second binary state.
Claim 33
Dependent Claim
61 words
The tape-read amplifier circuit according to claim 28 wherein said clipping circuit means comprises: a. a second reference amplifier responsive to a second reference voltage signal for providing a second reference voltage range; and b. a second comparator for comparing said first input signal with said second reference voltage range and generating said second input signal in said first binary state.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-07 | 1978-04-08 | 1978-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-07 | 1982-04-08 | 1982-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-07 | 1986-04-08 | 1986-10-08 | $7700.00 | Window Closed / Lapsed |