Signal processors for filtering applied signals

Claim 1

A signal processor adapted for responding to gating signals of a predetermined fixed interpulse period and of a duration substantially less than said interpulse period; and to an applied signal consisting of a sequence of contiguous pulses with each of said pulses having a duration equal to the period between said gating pulses, a substantially uniform amplitude during a predetermined portion of each pulse interval and with the amplitudes of the respective pulses being representative of the information content of said applied signal and with said gating pulses and the pulses of said applied signal being synchronized such that said gating pulses occur during said uniform amplitude portions of said applied signal pulses, said processor being further adapted for converting said applied signal to an output signal which is a reproduction of said applied signal but with a reduction in higher frequency signal components which are characteristic of the amplitude transitions between pulses which comprise said applied signal; said signal processor comprising: first means, having a first input circuit adapted for receiving said applied signal and a second input circuit and an output circuit, for providing at said output circuit a difference signal which is a function of the difference between the signals applied to its first and second input circuits; sample-and-hold means, having a gate signal input circuit adapted to receive said gating signals, for sampling the value of said difference signal during the periods of application of said gating signals, for storing said sampled value between sampling operations and for providing a sampled difference output signal which is representative of said stored sampled value; and integrating means, having an input circuit and an output circuit, for integrating signals applied to its input circuit; said integrating means having its input circuit coupled to receive said sampled difference output signal, and its output circuit coupled to the second input circuit of said first means; whereby said output signal from said processor is provided at the output circuit of said integrating means.