Compensated baseline circuit

Claim 2

Apparatus receiving the differential of a data signal subject to peak shift errors caused by pulse crowding, and supplying a compensated baseline signal useful in extracting the data content of the differentiated data signal, comprising means for recording the value of at least one positive peak and one negative peak of the differentiated data signal and means for producing a compensated baseline signal with a value dependent upon the recorded values of the positive and negative peaks of the differentiated data signal and falling beTween a pair of adjacent opposite polarity peaks.

Claim 3

The apparatus of claim 1 wherein the compensated baseline signal producing means comprises means for supplying a compensated baseline signal following the algebraic mean value of a positive peak and a negative peak of the differentiated data signal.

Claim 4

The apparatus of claim 1 wherein the baseline signal generator comprises a signal mean generator supplying a compensated baseline signal encoding the value of the algebraic mean of a positive peak and a negative peak of the differentiated data signal.

Claim 5

The apparatus of claim 1 wherein the baseline signal generator comprises a signal mean generator supplying a compensated baseline signal encoding the value of the algebraic mean of a positive peak and adjacent negative peak of the differentiated data signal.

Claim 6

The apparatus of claim 4, further comprising means for producing a modified compensated baseline signal falling between the compensated baseline signal and ground.

Claim 7

The apparatus of claim 5 wherein the compensated baseline signal modifying means comprises a pair of series-connected impedances connecting the compensated baseline signal to ground and supplying the modified signal at their connection point.

Claim 8

The apparatus of claim 6 wherein each impedance comprises a resistor.

Claim 9

The apparatus of claim 1 further comprising a positive peak recorder storing the value of a positive peak of the differentiated data signal, and a negative peak recorder storing the value of a negative peak of the differentiated data signal.

Claim 10

The apparatus of claim 8 wherein each peak recorder further comprises a capacitor, means for charging the capacitor to the peak differentiated data signal value to be recorded, and means for preventing discharge of the capacitor at greater than a predetermined rate until after the differentiated data signal has crossed the compensated baseline signal in a predetermined direction.

Claim 11

The apparatus of claim 9 wherein the charging means and discharge preventing means in combination comprise a first diode connecting the differentiated data signal source to the capacitor and driven into conduction by a differentiated data signal peak of the polarity to be stored on the capactior.

Claim 12

The apparatus of claim 10, wherein each peak recorder further comprises a current source supplying current of polarity similar to the differentiated data signal peaks to be stored on the capacitor, to the diode terminal connected to the differentiated data signal source.

Claim 13

The apparatus of claim 11, wherein each peak recorder further comprises a second diode connecting the differentiated data signal source to the junction of the current source and the first diode, which like diode terminals connected.

Claim 14

The apparatus of claim 9, wherein each peak recorder further comprises means for discharging the capacitor to reach a predetermined level after the differentiated data signal has crossed the compensated baseline signal in a predetermined direction.

Claim 15

The apparatus of claim 13 wherein each discharging means comprises a variable impedance connected across the capacitor terminals and entering a low impedance state responsive to the differentiated data signal crossing the compensated baseline signal in a predetermined direction.

Claim 16

The apparatus of claim 14 wherein the discharging means further comprises means for placing the variable impedance in a high impedance state a predetermined time after entering the low impedance state.

Claim 17

The apparatus of claim 14 wherein the discharging means further comprises a one-shot supplying a closure signal responsive to the second crossing of the compensated baseline signal following the previous issuance of the closure signal, and wherein the variable impedance comprises a switch closing responsive to the closure signal.

Claim 20

The apparatus of claim 17 wherein each variable impedance comprises a switch closing responsive to a closure signal; and a one-shot setting responsive to the changes in the differential comparator output causes by the differentiated data signal moving toward the peak stored by the recorder of which the one-shot is an element, and supplying a closure signal to the switch while set.

Claim 21

The apparatus of claim 14 further comprising a delay receiving the differentiated data signal and supplying the differentiated data signal delayed sufficiently to cause the delayed signal transition between two adjacent recorded peaks to cross the compensated baseline signal computed from them before the occurrence of the peak in the undelayed differentiated data signal following the later of the recorded peaks.

Claim 22

The apparatus of claim 19 wherein each variable impedance includes means for causing it to enter its high and low impedance states responsive to, respectively, first and second states of a closure signal and wherein each discharging means further comprises a logic element supplying the second state of the closure signal responsive to the delayed differentiated data signal crossing the baseline signal in the direction away from the peak stored in the associated capacitor and while the undelayed differentiated data signal is between the voltages on the capacitors, and the fifst state otherwise.

Claim 23

The apparatus of claim 19 further comprising a first comparator receiving the compensated baseline signal and the delayed differentiated data signal and supplying an output signal having first and second states respectively as the delayed differentiated data signal voltage is less than more positive than the baseline signal voltage; a second comparator receiving the undelayed differentiated data signal and the voltage across the capacitor storing the positive peaks and supplying an output signal having first and second states respectively as the capacitor voltage is less and more positive than the undelayed differentiated data signal; a third comparator receiving the undelayed differentiated data signal and the voltage across the capacitor storing the negative peaks and supplying an output signal having first and second states respectively as the capacitor voltage is less and more positive than the undelayed differentiated data signal; and wherein the variable impedance discharging the positive peak storing capacitor further comprises a first normally open switch element which is connected across the capacitor terminals, which receives the output of the first and second comparators, which closes responsive to the output of the first comparator changing from its second to its first state and which is open while the output of the second comparator is in its first state; and the variable impedance discharging the negative peak storing capacitor further comprises a second switch element which is connected across the capacitor terminals, which receives the output of the first and third comparators, which closes responsive to the output of the first comparator changing from its first to its second state and which is open while the output of the third comparator is in its second state.

Claim 24

The apparatus of claim 13 wherein each discharging means comprises a resistor connected across the corresponding capacitor.

Claim 25

The apparatus of claim 13 wherein each discharging means comprises a resistor connected across the corresponding capacitor and having a value allowing the capacitor to discharge to within a predetermined value of the lowest possible peak of the polarity stored by the capacitor.

Claim 26

The apparatus of claim 13 further comprising a delay circuit delaying the differentiated data signal by a predetermined amount, means for charging each capacitor to each delayed DDS peak of the polarity stored by it, as each peak occurs; and wherein eaCh discharging means comprises a resistor connected across the corresponding capacitor.

Claim 27

The apparatus of claim 13 wherein each discharging means comprises an impedance connected across the corresponding capacitor; and further comprising a delay circuit delaying the differentiated data signal by an interval substantially equal to the shortest time between any of its successive DDS peaks of opposite polarity, and means for charging each capacitor to the delayed differentiated data signal peak of the polarity stored by the capacitor.

Claim 28

The apparatus of claim 25 wherein the means for charging each capacitor to the delayed differentiated data signal peak comprises a diode connecting the delayed differentiated data signal to a capacitor and being forward biased by the occurrence of a delayed differentiated data signal peak of the polarity stored by the capacitor.

Claim 29

The apparatus of claim 26 further comprising a second diode and a current source associated with each peak recorder, the current source supplying current of polarity similar to the differentiated data signal peaks stored on the capacitor to the capacitor through the second diode to charge the capacitor to the peak of the delayed differentiated data signal and prevent capacitor discharge through the second diode.

Claim 30

The apparatus of claim 9 wherein a peak recorder further comprises means for maintaining constant current discharge of the capacitor therein sufficient to discharge the capacitor to within a predetermined voltage range prior to the occurence of each successive peak.

Claim 31

The apparatus of claim 9 further comprising an impedance discharging the positive peak storing capacitor into the negative peak storing capacitor at a rate sufficient to discharge the capacitors to within a predetermined voltage range prior to the occurrence of each successive peak.

Claim 32

The apparatus of claim 9 further comprising a constant discharge current regulator discharging the positive peak storing capacitor into the negative peak storing capacitor at a rate sufficient to discharge the capacitor to within a predetermined voltage range prior to the occurrence of each successive peak.

Claim 33

The apparatus of claim 9 further comprising a pair of impedances connected to provide a series path to discharge the positive peak storing capacitor into the negative peak storing capacitor at a rate sufficient to discharge the capacitors to within predetermined voltage ranges prior to each successive peak, and to supply the compensated baseline signal at the junction of the two impedances.

Claim 34

The apparatus of claim 31 wherein at least one impedance comprises a resistor.

Claim 35

The apparatus of claim 8 further comprising first and second impedances each having first and second terminals and each receiving at their first terminals respectively, the values recorded by the positive and negative peak recorders, and having their second terminals commonly connected and supplying thereat the compensated baseline signal.

Claim 36

The apparatus of claim 33 wherein at least one of the first and second impedances comprise a resistor.

Claim 37

The apparatus of claim 33 wherein the two impedances comprise equal-valued resistors.

Claim 40

The method of claim 36, wherein the peak recording steps further comprise the sTeps of recording every positive and every negative peak value, and the differentiated data signal delaying step further comprises delaying the differentiated data signal until the transition between adjacent peaks of opposite polarity starts within a predetermined time of occurrence of the earlier of the two adjacent peaks.

Claim 41

The method of claim 36 wherein the step of producing a compensated baseline signal further comprises the step of forming a signal following the algebraic mean of the adjacent recorded peaks.

Claim 42

Apparatus for digitizing a pulse-crowded data signal after differentiation of the data signal, comprising: a. a compensated baseline signal generator receiving the differentiated data signal and supplying a compensated baseline signal encoding a value between a first positive peak and an adjacent first negative peak of the differentiated data signal; b. means for delaying the differentiated data signal a time sufficient to permit the differentiated data signal transition between the first positive and first negative peaks to cross the compensated baseline signal; and c. a digitizer receiving the delayed differentiated data signal and the compensated baseline signal and generating the digitizer output signal and generating the digitizer output signal therefrom.

Claim 43

Apparatus for digitizing a pulse-crowded data signal after differentiation of the data signal, comprising: a. a compensated baseline signal generator receiving the differentiated data signal and supplying a compensated baseline signal encoding a value between a first positive peak and an adjacent first negative peak of the differentiated data signal; b. means for delaying the differentiated data signal a time sufficient to permit the differentiated data signal transition between the first positive and first negative peaks to cross the compensated baseline signal; and c. a digitizer receiving the delayed differentiated data signal and the compensated baseline signal and generating the digitizer output signal and generating the digitizer output signal therefrom.

Claim 44

The apparatus of claim 39 wherein the delay means further comprises a signal delay receiving the differentiated data signal and supplying this signal delayed by a time no longer than the shortest interval between adjacent, opposite polarity peaks of the differentiated data signal, and no shorter than the maximum interval between the occurrence of a first peak of the differentiated data signal and the instant when the differentiated data signal crosses the compensated baseline signal between the first peak and the opposite polarity peak immediately following the first peak.

Claim 45

The apparatus of claim 39 wherein the compensated baseline signal generator comprises means for providing a compensated baseline signal varying as a function of at least another peak of the differentiated data signal in addition to said first positive and negative peak.

Claim 46

The apparatus of claim 39 wherein the digitizer comprises: a. means for receiving the delayed differentiated data and the compensated baseline signals for supplying a compensated delayed differential data signal following the difference of the voltages of the delayed differentiated data and the compensated baseline signals; b. a reference voltage source; and c. a differential comparator receiving the compensated delayed differentiated data signal and the reference voltage, and supplying an output signal having first and second states when the compensated delayed differentiated data signal is respectively lesser and greater than the reference voltage.

Claim 47

The apparatus of claim 42 wherein the summing means comprises a voltage subtractor supplying an output whose instantaneous voltage equals the difference of the instantaneous voltage of the compensated baseline signal subtracted from that of the delayed differentiated data signal and wherein the reference voltage input of the comparator is grounded.

Claim 48

The apparatus of claim 39 including a delay receiving the differentiated data signal and supplying this signal delayed by an interval no longer than the shortest interval between adjacent opposite polarity peaks.