Analog information storage and retrieval system

Claim 2

In combination with a memory having a plurality of addressable storage locations, first means for addressing said storage locations in a predetermined cyclic sequence at a first rate, second means for addressing said storage locations in said predetermined cyclic sequence at a second rate, sensing means responsive to said first and second means for sensing the distance in said sequence between the locations addressed by said first and second means, and means controlled by said sensing means for selectively inhibiting the operation of said first means and said second means to maintain said distance in a predetermined range.

Claim 3

In combination, an analog storage register comprising a set of storage means, an input terminal, an output terminal, first switching means selectively operable to connect said input terminal to any of said storage means, second switching means selectively operable to connect any of said storage means to said output terminal, input address control means cyclically operable in response to a first series of applied signals to operate said first switching means to sequentially connect said input terminal to each of said storage meAns in a cyclic ordered sequence, output address control means cyclically operable in response to a second series of applied signals to operate said second switching means to sequentially connect said output terminal to each of said storage means in said cyclic ordered sequence and signal generating means controlled by said input and output address control means for producing a signal in accordance with the distance in said sequence between the storage means connected to said input terminal and the storage means connected to said output terminal.

Claim 4

In combination, an analog storage register comprising a set of storage means, an input terminal, an output terminal, first switching means selectively operable to connect said input terminal to any of said storage means, second switching means selectively operable to connect any of said storage means to said output terminal, input address control means cyclically operable in response to a first series of applied signals to operate said first switching means to sequentially connect said input terminal to each of said storage meAns in a cyclic ordered sequence, output address control means cyclically operable in response to a second series of applied signals to operate said second switching means to sequentially connect said output terminal to each of said storage means in said cyclic ordered sequence and signal generating means controlled by said input and output address control means for producing a signal in accordance with the distance in said sequence between the storage means connected to said input terminal and the storage means connected to said output terminal.

Claim 5

The apparatus of claim 2, in which said signal generating means comprises a set of diodes, one for each of said storage means, means connecting said diodes in series aiding relationship in a closed series path so that there is a one-to-one correspondence between said storage means and the junctions of said diodes, sensing means comprising a pair of terminals and means responsive to an electrical characteristic of the path between said terminals for producing a signal in accordance with said characteristic, third switching means actuated by said input address control means for connecting one of said terminals to the junction between said diodes corresponding to the storage means connected to said input terminal, and fourth switching means actuated by said output address control means for connecting the other of said terminals to the junction between said diodes corresponding to the storage means connected to said output terminal.

Claim 6

Compensating means, comprising means for simultaneously reproducing an information signal and a reference signal from a record on which the signals have been simultaneously recorded, a sequence of addressable storage locations, input sampling means settable to first and second states and responsive to said signals in its first stage for storing samples of said reproduced information signal in said memory in a cyclic ordered sequence of said storage locations at a rate determined by the frequency of said reproduced reference signal, an output terminal, output signal producing means settable to first and second stages and effective in its first state to apply samples from said memory to said output terminal at a constant rate from storage locations addressed in said cyclic ordered sequence, means controlled by said input sampling means and said output signal producing means for setting said input sampling means to its first or its second state according as the difference between the number of samples stored in said memory and the number of different samples applied to said output terminal does not or does exceed a predetermined positive number, respectively, and means controlled by said input sampling means and said output signal producing means for setting said output signal generating means to its first or its second state according as said difference does not or does exceed a predetermined negative number, respectively.

Claim 7

Compensating means, comprising means for simultaneously reproducing an information signal and a reference signal from a record on which the signals have been simultaneously recorded, a sequence of addressable storage locations, input sampling means settable to first and second states and responsive to said signals in its first stage for storing samples of said reproduced information signal in said memory in a cyclic ordered sequence of said storage locations at a rate determined by the frequency of said reproduced reference signal, an output terminal, output signal producing means settable to first and second stages and effective in its first state to apply samples from said memory to said output terminal at a constant rate from storage locations addressed in said cyclic ordered sequence, means controlled by said input sampling means and said output signal producing means for setting said input sampling means to its first or its second state according as the difference between the number of samples stored in said memory and the number of different samples applied to said output terminal does not or does exceed a predetermined positive number, respectively, and means controlled by said input sampling means and said output signal producing means for setting said output signal generating means to its first or its second state according as said difference does not or does exceed a predetermined negative number, respectively.

Claim 8

In combination, transducer means for reproducing from a record an information signal and a reference signal recorded on the record, an addressable memory, sampling means controlled by said transducer means for storing samples of a reproduced information signal in said memory in a cyclic ordered sequence of addresses at a rate determined by the frequency of a reproduced reference signal, an output terminal, output signal producing means for sequentially supplying output signals to said output terminal from said ordered sequence of addresses at a constant rate, means controlled by said sampling means and said output signal producing means for producing a control signal in accordance with the difference between the addresses at which samples are being stored and supplied to said output terminal, respectively, means responsive to said control signal for inhibiting the operation of said sampling means when the number of samples stored in said memory exceeds the number of samples supplied to said output terminal by a predetermined amount, and means responsive to said control signAl for inhibiting the operation of said output signal producing means when the number of samples applied to said output terminal exceeds the number of samples stored in said memory by a predetermined amount.

Claim 9

In combination, transducer means for reproducing from a record an information signal and a reference signal recorded on the record, an addressable memory, sampling means controlled by said transducer means for storing samples of a reproduced information signal in said memory in a cyclic ordered sequence of addresses at a rate determined by the frequency of a reproduced reference signal, an output terminal, output signal producing means for sequentially supplying output signals to said output terminal from said ordered sequence of addresses at a constant rate, means controlled by said sampling means and said output signal producing means for producing a control signal in accordance with the difference between the addresses at which samples are being stored and supplied to said output terminal, respectively, means responsive to said control signal for inhibiting the operation of said sampling means when the number of samples stored in said memory exceeds the number of samples supplied to said output terminal by a predetermined amount, and means responsive to said control signAl for inhibiting the operation of said output signal producing means when the number of samples applied to said output terminal exceeds the number of samples stored in said memory by a predetermined amount.

Claim 10

In a compensator for reducing frequency shifts in an information signal with the aid of a reference signal that has experienced the same frequency shifts from an initially predetermined frequency, a memory, first means for entering samples of the information signal into successive locations in said memory at a rate determined by the frequency of the reference signal, an output terminal, second means for applying samples from said successive locations in said memory to said output terminal at a rate determined by said predetermined frequency, and means responsive to the difference between the locations in said memory in which samples are being entered and the locations from which samples are being applied to said output terminal for inhibiting the operation of said first means or said second means according as the locations at which samples are being entered approach the locations from which samples are being applied to said output terminal or conversely, respectively.

Claim 11

In a compensator for reducing frequency shifts in an information signal with the aid of a reference signal that has experienced the same frequency shifts from an initially predetermined frequency, a memory, first means for entering samples of the information signal into successive locations in said memory at a rate determined by the frequency of the reference signal, an output terminal, second means for applying samples from said successive locations in said memory to said output terminal at a rate determined by said predetermined frequency, and means responsive to the difference between the locations in said memory in which samples are being entered and the locations from which samples are being applied to said output terminal for inhibiting the operation of said first means or said second means according as the locations at which samples are being entered approach the locations from which samples are being applied to said output terminal or conversely, respectively.

Claim 12

In combination, a memory, sampling means responsive to an applied information signal and controlled by an applied reference signal for storing samples of said information signal in said memory at a cyclic ordered sequence of addresses at a rate determined by the frequency of said reference signal, output signal producing means for extracting samples stored in said memory from said cyclic ordered sequence of addresses at a constant rate, address difference detecting means responsive to the difference between the storage and extraction addresses for inhibiting the operation of said sampling means or said output signal producing means according as said storage address is overtaking said extraction address, or conversely, respectively.

Claim 13

In combination, a memory, sampling means responsive to an applied information signal and controlled by an applied reference signal for storing samples of said information signal in said memory at a cyclic ordered sequence of addresses at a rate determined by the frequency of said reference signal, output signal producing means for extracting samples stored in said memory from said cyclic ordered sequence of addresses at a constant rate, address difference detecting means responsive to the difference between the storage and extraction addresses for inhibiting the operation of said sampling means or said output signal producing means according as said storage address is overtaking said extraction address, or conversely, respectively.

Claim 14

In combination, transducer means for simultaneously reproducing an information signal and a reference signal from a record moving relative to said transducer means, said signals being reproduced at frequencies dependent on the speed of said record relative to said transducer means, first filter means connected to said transducer means for selectively producing said reproduced information signal, second filter means connected to said transducer means for selectively producing said reproduced reference signal, an analog storage register comprising a predetermined number of storage means, first switching means connected to said first filter means and selectively operable to apply said reproduced information signal to any one of said storage means, first cyclically operable means responsive to a series of applied signals to operate said first switching means to sequentially apply said information signal to each of said storage means in a cyclic ordered sequence, an output terminal, second switching means operable to connect any one of said storage means to said output terminal, second cyclically operable means responsive to a series of applied signals to sequentially connect each of said storage means to said output terminal in said cyclic ordered sequence, sensing means responsive to the relative locations in said sequence of the storage means connected to said first filter means and the storage means connected to said output terminal for producing a control signal indicative of said difference, means connected to said second filter means and said sensing means for applying signals to said first cyclically operable means at a rate determined by the frequency of said reproduced reference signal when said difference is in a first range, and means controlled by said sensing means for applying signals to said second cyclically operable means at a constant rate when said difference is in a second range.

Claim 15

In combination, transducer means for simultaneously reproducing an information signal and a reference signal from a record moving relative to said transducer means, said signals being reproduced at frequencies dependent on the speed of said record relative to said transducer means, first filter means connected to said transducer means for selectively producing said reproduced information signal, second filter means connected to said transducer means for selectively producing said reproduced reference signal, an analog storage register comprising a predetermined number of storage means, first switching means connected to said first filter means and selectively operable to apply said reproduced information signal to any one of said storage means, first cyclically operable means responsive to a series of applied signals to operate said first switching means to sequentially apply said information signal to each of said storage means in a cyclic ordered sequence, an output terminal, second switching means operable to connect any one of said storage means to said output terminal, second cyclically operable means responsive to a series of applied signals to sequentially connect each of said storage means to said output terminal in said cyclic ordered sequence, sensing means responsive to the relative locations in said sequence of the storage means connected to said first filter means and the storage means connected to said output terminal for producing a control signal indicative of said difference, means connected to said second filter means and said sensing means for applying signals to said first cyclically operable means at a rate determined by the frequency of said reproduced reference signal when said difference is in a first range, and means controlled by said sensing means for applying signals to said second cyclically operable means at a constant rate when said difference is in a second range.

Claim 16

A frequency compensator, comprising reproducing means for simultaneously reproducing an information signal and a reference signal from a record, memory means comprIsing a plurality of storage locations, sampling means controlled by said reproducing means for sequentially storing samples of said reproduced information signal in said storage locations at a rate determined by the frequency of said reproduced reference signal, output signal producing means for producing a signal sequentially determined by the contents of said storage locations at a constant rate, means for sensing the approach of the locations in which samples are stored by said sampling means to the locations determining said output signal for interrupting the operation of said sampling means to prevent a crossover in the memory when the sampling rate exceeds said constant rate, and means for sensing the approach of the locations determining said output signal to the locations in which samples are stored by said sampling means for interrupting the operation of said output signal producing means to prevent a crossover in the memory when said constant rate exceeds the sampling rate.

Claim 17

A frequency compensator, comprising reproducing means for simultaneously reproducing an information signal and a reference signal from a record, memory means comprIsing a plurality of storage locations, sampling means controlled by said reproducing means for sequentially storing samples of said reproduced information signal in said storage locations at a rate determined by the frequency of said reproduced reference signal, output signal producing means for producing a signal sequentially determined by the contents of said storage locations at a constant rate, means for sensing the approach of the locations in which samples are stored by said sampling means to the locations determining said output signal for interrupting the operation of said sampling means to prevent a crossover in the memory when the sampling rate exceeds said constant rate, and means for sensing the approach of the locations determining said output signal to the locations in which samples are stored by said sampling means for interrupting the operation of said output signal producing means to prevent a crossover in the memory when said constant rate exceeds the sampling rate.

Claim 18

Means for reproducing an analog signal recorded on a record simultaneously with a constant frequency pilot signal, comprising transducer means, drive means for moving the record relative to said transducer means to cause said transducer means to reproduce the recorded signals, an input terminal, an output terminal, a series of addressable analog storage means, means connecting said transducer means to said input terminal to apply said reproduced analog signal to said input terminal, input addressing means connected to said transducer means and responsive to said reproduced pilot signal for sequentially addressing said storage means from said input terminal to store samples of said analog signal in said storage means at a rate determined by the frequency of said reproduced pilot signal, a constant frequency oscillator, output addressing means controlled by said oscillator for sequentially addressing said output terminal from said storage means at a rate determined by the frequency of said oscillator to produce an output signal determined by the stored samples, and address difference detecting means responsive to the difference between the input and output addresses for interrupting the operation of said input addressing means or said output addressing means according as said input address is about to overtake said output address, or conversely, respectively.

Claim 19

Means for reproducing an analog signal recorded on a record simultaneously with a constant frequency pilot signal, comprising transducer means, drive means for moving the record relative to said transducer means to cause said transducer means to reproduce the recorded signals, an input terminal, an output terminal, a series of addressable analog storage means, means connecting said transducer means to said input terminal to apply said reproduced analog signal to said input terminal, input addressing means connected to said transducer means and responsive to said reproduced pilot signal for sequentially addressing said storage means from said input terminal to store samples of said analog signal in said storage means at a rate determined by the frequency of said reproduced pilot signal, a constant frequency oscillator, output addressing means controlled by said oscillator for sequentially addressing said output terminal from said storage means at a rate determined by the frequency of said oscillator to produce an output signal determined by the stored samples, and address difference detecting means responsive to the difference between the input and output addresses for interrupting the operation of said input addressing means or said output addressing means according as said input address is about to overtake said output address, or conversely, respectively.

Claim 20

The apparatus of claim 10, further comprising means responsive to said address difference detecting means for controlling said drive means to move the record relative to said transducer means at a speed at which the average frequency of said reproduced pilot signal equals the frequency at which the pilot signal was recorded.

Claim 21

The apparatus of claim 10, in which said address difference detecting means comprises a set of diodes, one for each of said storage means, said diodes being connected together in series aiding relationship in a closed series path so that there is a one-to-one correspondence between said storage means and the junctions between said diodes, first and second sensing terminals, means responsive to the voltage between said terminals for producing a control signal determined by said voltage, means controlled by said input addressing means for connecting said first sensing terminal to junctions between said diodes corresponding to the storage means addressed by said input addressing means, means controlled by said output addressing means for connecting said second sensing termainl to junctions between said diodes corresponding to the storage means addressed by said output addressing means, and means responsive to said control signal for interrupting the operation of said input addressing means or said output addressing means according as said control signal is in a first or a second range, respectively.

Claim 22

Apparatus for correcting phase shifts in an analog signal with the aid of a reference signal having corresponding phase shifts from a predetermined frequency, said apparatus comprising, an input terminal, an output terminal, a bank of capacitors, first switching means cyclically operable in response to a train of applied signals to selectively connect each of said capacitors to said input terminal in a cyclic ordered sequence to store voltages corresponding to samples of the voltage on said input terminal, second switching means cyclically operable in response to a train of applied signals to selectively connect each of said capacitors to said output terminal in said cyclic ordered sequence to produce a voltage on said output terminal corresponding to the voltages stored by the capacitor, means for applying the analog signal to said input terminal, first signal generating means for receiving the reference signal and producing a train of signals at a rate determined by the frequency of the reference signal, second signal generating means for producing a train of signals at a constant rate, a set of diodes, one for each capacitor, said diodes being connected together in series aiding relationship in a closed series path so that there is a one-to-one correspondence between the junctions of said diodes and the capacitors, first and second sensing terminals, sensing means connected to said sensing terminals for producing a control signal determined by the voltage between said terminals, means controlled by said first switching means for connecting said first sensing terminal to the junction between said diodes corresponding to the capacitor to which said input terminal is connected, means controlled by said second switching means for connecting said second sensing terminal to the junction between said diodes corresponding to the capacitor to which said output terminal is connected, first gating means connected to said first signal generating means and enabled by said control signal in a first range thereof for applying the signals from said first signal generating means to said first switching means when enabled, and second gating means enabled by said control signal in a second range including a portion of said first range and connected to said second signal generating means for applying the signals produced by said second signal generating means to said second switching means when enabled.

Claim 23

Apparatus for correcting phase shifts in an analog signal with the aid of a reference signal having corresponding phase shifts from a predetermined frequency, said apparatus comprising, an input terminal, an output terminal, a bank of capacitors, first switching means cyclically operable in response to a train of applied signals to selectively connect each of said capacitors to said input terminal in a cyclic ordered sequence to store voltages corresponding to samples of the voltage on said input terminal, second switching means cyclically operable in response to a train of applied signals to selectively connect each of said capacitors to said output terminal in said cyclic ordered sequence to produce a voltage on said output terminal corresponding to the voltages stored by the capacitor, means for applying the analog signal to said input terminal, first signal generating means for receiving the reference signal and producing a train of signals at a rate determined by the frequency of the reference signal, second signal generating means for producing a train of signals at a constant rate, a set of diodes, one for each capacitor, said diodes being connected together in series aiding relationship in a closed series path so that there is a one-to-one correspondence between the junctions of said diodes and the capacitors, first and second sensing terminals, sensing means connected to said sensing terminals for producing a control signal determined by the voltage between said terminals, means controlled by said first switching means for connecting said first sensing terminal to the junction between said diodes corresponding to the capacitor to which said input terminal is connected, means controlled by said second switching means for connecting said second sensing terminal to the junction between said diodes corresponding to the capacitor to which said output terminal is connected, first gating means connected to said first signal generating means and enabled by said control signal in a first range thereof for applying the signals from said first signal generating means to said first switching means when enabled, and second gating means enabled by said control signal in a second range including a portion of said first range and connected to said second signal generating means for applying the signals produced by said second signal generating means to said second switching means when enabled.