US3571801A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data transfer system
Assignee: National Aeronautics and Space Administration
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Filing: 1966-06-03
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Granted: 1971-03-23
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Expires: 1986-06-03
Abstract
Abstract A data acquisition system effects readout by clocking data from a tape into a storage register under control of a tape shift register. Data is clocked out of the data storage register by a clock shift register. A system clock drives a shift register and divide by 10 circuit which both regulates the translation of the data clocked out of the storage register from a parallel to a precise serial format, and also drives the clock shift register. Output signals from the tape shift register and from the clock shift register drive a digital servocontrol circuit to regulate the speed of the motor which drives the tape transport, to insure the data storage register neither ''''overflows'''' nor ''''runs dry.
Inventors
- 👤 John E Coolidge
- 👤 John F Kinkel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:52
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/008; G11B5/00813
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
338 words
In a data transfer system including a tape transport, a magnetic tape medium for storing both data information and timing information thereon, and a motor operative to drive the tape transport: a data storage register for accepting said data information from the tape medium subject to jitter as the data is gated in by said timing information and for discharging the data, a tape shift register for receiving said timing information from the magnetic tape medium to regulate the passage of said data information from the magnetic tape medium into said data storage register, and for providing a first set of timing signals in accordance with the cycling of said tape shift register, a clock shift register for receiving precise timing signals to regulate the read out of the data information from the data storage register, and for providing a second set of timing signals in accordance with the cycling of said clock shift register; a readout unit comprising a temporary buffer storage array for receiving data information read out of said data sTorage register, and a shift register and divide by 10 circuit coupled to said temporary buffer storage array, operative in accordance with receipt of precise timing signals to sequentially gate the data information out of said temporary buffer storage array and to provide precise timing signals to said storage register each time said shift register and divide by 10 circuit is cycled; and a control circuit, having an output terminal coupled to said motor, a first input connection for receiving said first set of timing signals indicating the variable rate at which data is transferred from the tape recorder into the data storage register, and a second input connection for receiving said second set of timing signals indicating the precise rate at which data is transferred from the data storage register into the temporary buffer storage array, said control circuit regulating energization of the motor at a speed such that the data storage register always has data stored therein and neither overflows nor runs dry.
Claim 2
Dependent Claim
338 words
In a data transfer system including a tape transport, a magnetic tape medium for storing both data information and timing information thereon, and a motor operative to drive the tape transport: a data storage register for accepting said data information from the tape medium subject to jitter as the data is gated in by said timing information and for discharging the data, a tape shift register for receiving said timing information from the magnetic tape medium to regulate the passage of said data information from the magnetic tape medium into said data storage register, and for providing a first set of timing signals in accordance with the cycling of said tape shift register, a clock shift register for receiving precise timing signals to regulate the read out of the data information from the data storage register, and for providing a second set of timing signals in accordance with the cycling of said clock shift register; a readout unit comprising a temporary buffer storage array for receiving data information read out of said data sTorage register, and a shift register and divide by 10 circuit coupled to said temporary buffer storage array, operative in accordance with receipt of precise timing signals to sequentially gate the data information out of said temporary buffer storage array and to provide precise timing signals to said storage register each time said shift register and divide by 10 circuit is cycled; and a control circuit, having an output terminal coupled to said motor, a first input connection for receiving said first set of timing signals indicating the variable rate at which data is transferred from the tape recorder into the data storage register, and a second input connection for receiving said second set of timing signals indicating the precise rate at which data is transferred from the data storage register into the temporary buffer storage array, said control circuit regulating energization of the motor at a speed such that the data storage register always has data stored therein and neither overflows nor runs dry.
Claim 3
Dependent Claim
230 words
In a data reproducing system including a tape transport, a magnetic tape for storing both data signals and timing signals thereon, and a motor for driving the tape transport: a storage register for accepting said data signals from the magnetic tape as the data, then subjected to jitter-type error, is gated in in parallel format by said timing signals; a parallel-to-serial converter including a temporary buffer storage array for receiving the data signals in parallel format from said storage register, and a shift register and divide by 10 circuit for receiving precise timing signals from a master source and for gating the data signals out of said temporary buffer storage array at a precise, jitter-free rate in accordance with receipt of said precise timing signals, and for passing a timing signal to said storage register each time said parallel-to-serial converter is cycled; and a digital servocontrol circuit, coupled to said motor, having a first input connection for receiving first timing signals from said storage register connoting the rate at which data is gated into said storage register, and a second input connection for receiving second timing signals from said storage register connoting the rate at which data is gated out of said storage register, thereby to drive the motor at a speed such that the storage register always has data stored therein, and the register neither overflows nor runs dry.
Claim 4
Dependent Claim
230 words
In a data reproducing system including a tape transport, a magnetic tape for storing both data signals and timing signals thereon, and a motor for driving the tape transport: a storage register for accepting said data signals from the magnetic tape as the data, then subjected to jitter-type error, is gated in in parallel format by said timing signals; a parallel-to-serial converter including a temporary buffer storage array for receiving the data signals in parallel format from said storage register, and a shift register and divide by 10 circuit for receiving precise timing signals from a master source and for gating the data signals out of said temporary buffer storage array at a precise, jitter-free rate in accordance with receipt of said precise timing signals, and for passing a timing signal to said storage register each time said parallel-to-serial converter is cycled; and a digital servocontrol circuit, coupled to said motor, having a first input connection for receiving first timing signals from said storage register connoting the rate at which data is gated into said storage register, and a second input connection for receiving second timing signals from said storage register connoting the rate at which data is gated out of said storage register, thereby to drive the motor at a speed such that the storage register always has data stored therein, and the register neither overflows nor runs dry.
Claim 5
Dependent Claim
112 words
A data reproducing system as claimed in claim 2 in which said storage register includes a tape shift register having an input circuit for receiving said timing signals from the magnetic tape and an output circuit for passing the first timing signals to said digital servocontrol circuit to indicate the rate at which data is shifted into the storage register, and a clock shift register having an input circuit for receiving said timing signals from the shift register and divide by 10 circuit and an output circuit for passing the second timing signals to said digital servocontrol circuit to indicate the rate at which data is shifted out of the storage register.
Claim 6
Dependent Claim
291 words
A data reproducing system as claimed in claim 2 in which said storage register includes: a data storage register including a plurality of signal storage stages intercoupled in a matrix having a first number of rows and a second number of columns, including a number of input conductors corresponding to said first number and respectively coupled to the rows of storage stages for shifting data signals into said data storage register in parallel format, and a number of output conductors also corresponding to said first number and respectively coupled to the rows of storage stages for shifting data signals out of said storage register in parallel format; a tape shift register comprising a number of shift stages corresponding to said second number, at least one input conductor for receiving the timing signals from said magnetic tape, a plurality of output conductors respectively coupled between said Shift stages and the columns of storage stages in said matrix for regulating the shifting in of data signals over said data storage register input conductors, and another output conductor for passing said first timing signals to the digital servocontrol circuit as said tape shift register is cycled; and a clock shift register comprising a number of shift stages also corresponding to said second number, at least one input conductor for receiving said timing signals from the shift register and divide by 10 circuit, a plurality of output conductors respectively coupled between said shift stages in the clock shift register and the columns of storage stages in said matrix for regulating the shifting out of data signals over said data storage register output conductors, and another output conductor for passing said second timing signals to the digital servocontrol circuit as said clock shift register is cycled.
Claim 7
Dependent Claim
105 words
A data reproducing system as claimed in claim 2 in which said digital servo control circuit comprises a flip-flop stage which is changed from a first state to a second state in timed relation with receipt of said second timing signals from the storage register and which is returned from said second state to said first state in timed relation with receipt of said first timing signals from the storage register, to control energization of said motor for the appropriate time interval to maintain the level of data signals in said storage register between proper levels so that the register neither overflows nor runs dry.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-22 | 1974-09-21 | 1975-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-22 | 1978-09-21 | 1979-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-22 | 1982-09-21 | 1983-03-23 | $7700.00 | Window Closed / Lapsed |