Bifrequency controlled analog shift register speech processor

Claim 1

A processor for speech signals or the like comprising: a single serial analog shift register having a predetermined plurality of stages with a signal input terminal for the first stage; means for apply to said input terminal a frequency altered speech signal having frequency components altered by a given ratio; means for clocking said analog shift register at a first clock frequency selected in relation to the number of said stages to provide predetermined maximum delay required for processing said frequency altered speech signal as said input signal values are shifted successively through the stages of said register; means for clocking signals sequentially from the serial stages of said register at a second clock frequency related to said first clock frequency by said ratio by sampling the signal train stored in the stages of said register, both of said means for clocking operating concurrently on said analog shift register; means for combining the signals clocked sequentially from the stages of said register to produce a frequency transformed version of the speech signal applied to said input terminal with original frequency components restored; and means responsive to the combined signals for producing a replica of said speech signal.