High voltage bipolar semiconductor device and integrated circuit using the same and method

Claim 2

In an active semiconductor device, a semiconductor body having a planar surface, a first region of a first conductivity type formed in the body, a second region of a second conductivity type formed in the body within the first region and forming a first P-N junction, at least a portion of which extends to the surface, a layer of insulating material disposed on said planar surface and generally covering said portion of the junction extending to the surface, contact elements extending through said insulating layer and making contact with at least one of said regions and metallic means serving as a field plate disposed on said insulating layer and covering a substantial portion of said first region, said metallic means being physically and electrically split in at least one point to provide a space therebetween, said metallic means being electrically isolated from said first region, and lead means carried by said insulating layer in contact with said metallic means and said contact elements, at least a portion of said lead means passing through said space.

Claim 3

A device as in claim 1 wherein said body has an epitaxial layer formed thereon and wherein said first and second regions are formed in said epitaxial layer.

Claim 4

A semiconductor device as in claim 1 together with a third region of said first conductivity type formed within said second region and forming a second P-N junction, at least a portion of which extends to the surface together with a contact element for making contact to said third region.

Claim 5

A semiconductor device as in claim 3 wherein said metallic means and said lead means lie in a single plane.

Claim 6

A semiconducTor device as in claim 1 wherein said field plate is formed in at least two separate parts and wherein one of said parts is connected to one of said contact elements and the other of said parts is connected to another of said contact elements.

Claim 7

A semiconductor device as in claim 1 wherein said metallic means substantially surrounds the portion of said second region which lies on the planar surface of the semiconductor body.

Claim 8

A semiconductor device as in claim 1, together with means for biasing said device to produce a depletion region under said metallic means, and, wherein each space has a width which is less than twice the depth of the depletion layer.

Claim 9

In an integrated circuit, a semiconductor body having a planar surface, means carried by the body for forming a plurality of isolated islands on the body, a plurality of active and passive devices formed in said islands, at least one of said islands having a high voltage device formed therein, said high voltage active device comprising a first region of a first conductivity type formed in said one island, a second region of a second conductivity type formed in said island to provide a first P-N junction which extends to said planar surface, a layer of insulating material disposed on the planar surface of said body and over said junction, contact elements extending through said insulating layer and making contact with at least certain of said regions of said device, field plate means carried by said insulating layer and generally overlying a substantial portion of the first region, said field plate means with a voltage thereon serving to push the majority carriers away from the surface and to cause the depletion layer to be moved into the bulk of the semiconductor body, said field plate means being physically and electrically split in at least one point to provide a space therebetween, said field plate being electrically isolated from said first region and lead means carried by said layer of insulating material and making contact with said contact elements and said field plate means, at least a portion of said lead means passing through said space.

Claim 10

In an integrated circuit, a semiconductor body having a planar surface, means carried by the body for forming a plurality of isolated islands on the body, a plurality of active and passive devices formed in said islands, at least one of said islands having a high voltage device formed therein, said high voltage active device comprising a first region of a first conductivity type formed in said one island, a second region of a second conductivity type formed in said island to provide a first P-N junction which extends to said planar surface, a layer of insulating material disposed on the planar surface of said body and over said junction, contact elements extending through said insulating layer and making contact with at least certain of said regions of said device, field plate means carried by said insulating layer and generally overlying a substantial portion of the first region, said field plate means with a voltage thereon serving to push the majority carriers away from the surface and to cause the depletion layer to be moved into the bulk of the semiconductor body, said field plate means being physically and electrically split in at least one point to provide a space therebetween, said field plate being electrically isolated from said first region and lead means carried by said layer of insulating material and making contact with said contact elements and said field plate means, at least a portion of said lead means passing through said space.

Claim 11

An integrated circuit as in claim 8 wherein a third region of said first conductivity type is formed in said island within said second region and forming a second P-N junction which extends to the surface and wherein said field plate means generally circumscribes said P-N junction at said surface.

Claim 12

An integrated circuit as in claim 8 wherein said isolation is formed by dielectric isolation.

Claim 13

An integrated circuit as in claim 8 wherein said isolation is formed by diffused junction isolation.

Claim 14

An integrated circuit as in claim 8 wherein said semiconductor body is provided with an epitaxial layer and wherein said active and passive devices are formed in said epitaxial layer.

Claim 15

An integrated circuit as in claim 8 wherein said isolation is formed by a P-N junction which extends downwardly from the surface through the epitaxial layer together with additional field plate means disposed on the insulating layer and generally covering a substantial portion of the first region and generally overlying the depletion layer which is formed between the first region and the P-N junction utilized for isolation.

Claim 16

An integrated circuit as in claim 8 wherein said high voltage active device is a diode.

Claim 17

An integrated circuit as in claim 8 wherein said high voltage active device is a transistor together with a third region of said first conductivity type disposed within said second region forming a second P-N junction, at least a portion of which extends to the surface together with an additional contact element for making contact with said third region.

Claim 18

An integrated circuit as in claim 8 wherein said field plate means is formed in at least two parts and wherein at least certain of said parts of said field plate means are formed integral with said lead means.