Field effect transistor linear amplifier with clocked biasing means

Claim 2

In a linear amplifier having an input terminal and an outPut terminal comprising a load device, a supply voltage and a first semiconductor switching device having a control terminal and an output circuit, said output circuit of said switching device being operatively connected in series with said load device across said voltage supply, said control terminal being operatively connected to said input terminal and said output terminal being operatively connected to the junction between said load device and said first switching device, the improvement comprising means for operatively connecting said output terminal to said input terminal during a first clock interval and for feeding back a portion of said supply voltage to said input terminal during said first clock interval and means for storing said portion of said supply voltage during said first clock interval and applying said stored portion of said supply voltage to said input terminal during a second clock interval to maintain the appropriate bias on said first switching device during said second clock interval, the magnitude of said portion of said supply voltage being dependent upon the operating characteristics of said first switching device and the resistance of said load device.

Claim 3

The linear amplifier of claim 1, wherein said first semiconductor switching device is a metal oxide silicon field effect transistor, said control terminal thereof comprising its gate and the output circuit thereof defined by its source and drain terminals, said portion of said supply voltage being a function of the threshold voltage of said field effect transistor.

Claim 4

The linear amplifier of claim 2, wherein said second semiconductor switching device comprises a second metal oxide silicon field effect transistor having its drain terminal connected to the drain terminal of said first field effect transistor and its source terminal operatively connected to the gate terminal of said first field effect transistor, said second field effect transistor being effective to reset said linear amplifier during each complete clock cycle, thereby to prevent blocking from over voltage at said input terminal.

Claim 5

The linear amplifier of claim 3, wherein said storage means comprises a storage capacitor operatively connected between the source and gate terminals of said field effect transistor.

Claim 6

The linear amplifier of claim 1, wherein said load device is a resistor.

Claim 7

The linear amplifier of claim 1, further comprising a second supply voltage, wherein said load device comprises a third semiconductor switching device having its output circuit operatively connected in series with said first semiconductor switching device and having a control terminal operatively connected to said second supply voltage.

Claim 8

The linear amplifier of claim 6, wherein said second supply voltage comprises a second source of a timed clock signal.

Claim 9

The linear amplifier of claim 6, wherein said first semiconductor switching device is a metal oxide silicon field effect transistor, said control terminal thereof comprising its gate and the output circuit thereof defined by its source and drain terminals, said portion of said supply voltage being a function of the threshold voltage of said field effect transistor.

Claim 10

The linear amplifier of claim 8, wherein said storage means comprises a storage capacitor operatively connected between the source and gate terminals of said field effect transistor.

Claim 11

The linear amplifier of claim 9, wherein said second supply voltage comprises a second source of a timed clock signal.

Claim 12

The linear amplifier of claim 8, wherein said second semiconductor switching device comprises a second metal oxide silicon field effect transistor having its drain terminal connected to the drain terminal of said first field effect transistor and its source terminal operatively connected to the gate terminal of said first field effect transistor, said second field effect transistor being effective to reset said linear amplifier during each complete clock cycle, thereby to prevent Blocking from over voltage at said input terminal.

Claim 13

The amplifier of claim 1 wherein said storage means comprises a capacitor operatively connected to said control terminal of said first switching device, said capacitor having a value of capacitance such that, in conjunction with the magnitude of the said supply voltage, the resistance of said load device and the geometry and operating characteristics of said first switching device, it will charge through said feedback means during said first clock interval to a voltage level effective to bias said first switching device substantially to its operative linear amplification range and will substantially maintain said first switching device so biased during said second clock interval.

Claim 14

The linear amplifier of claim 12, wherein said first switching device comprises a field effect transistor having a source terminal and a gate terminal and wherein said storage means comprises a storage capacitor operatively connected between said source and gate terminals of said field effect transistor.

Claim 15

A linear amplifier having a supply voltage, an input terminal, an output terminal and a plurality of inverter stages, each such inverter stage comprising a semiconductor switching device having a control terminal and an output circuit, a load device, said output circuit of said switching device being connected in series with said load device across said voltage supply, the control terminal of the switching device of said first stage being operatively connected to said input terminal, the control terminals of the switching devices of succeeding stages being operatively connected to the junction between the switching device and load device of the preceding stage, said output terminal being operatively connected to the junction between said switching device and said load device of said last stage, and clocked feedback means for operatively connecting said output terminal and said input terminal during a first clock interval and effective to feed back a portion of said supply voltage to said input terminal during said first clock interval to automatically bias the switching device of said first stage to its linear amplification region, said portion of said supply voltage being dependent upon the operating characteristics of said semiconductor switching devices and the resistance of said load devices, and to thereafter isolate said input terminal from said output terminal during a second clock interval.

Claim 16

A linear amplifier having a supply voltage, an input terminal, an output terminal and a plurality of inverter stages, each such inverter stage comprising a semiconductor switching device having a control terminal and an output circuit, a load device, said output circuit of said switching device being connected in series with said load device across said voltage supply, the control terminal of the switching device of said first stage being operatively connected to said input terminal, the control terminals of the switching devices of succeeding stages being operatively connected to the junction between the switching device and load device of the preceding stage, said output terminal being operatively connected to the junction between said switching device and said load device of said last stage, and clocked feedback means for operatively connecting said output terminal and said input terminal during a first clock interval and effective to feed back a portion of said supply voltage to said input terminal during said first clock interval to automatically bias the switching device of said first stage to its linear amplification region, said portion of said supply voltage being dependent upon the operating characteristics of said semiconductor switching devices and the resistance of said load devices, and to thereafter isolate said input terminal from said output terminal during a second clock interval.

Claim 17

The linear amplifier of claim 14, further comprising capacitive storage means operatively connected to the control terminal of the switching device of said first stage and adapted to be charged to the level of said output signal during said first clock interval and to maintain said control terminal of the switching device of said first stage biased to said last mentioned level during said second clock interval.

Claim 18

The linear amplifier of claim 14, wherein said semiconductor switching device is a metal oxide silicon field effect transistor, said control terminal thereof comprising its gate and the output circuit thereof being defined by its source and drain, the output signal fed back to said input terminal during said first clock interval being a function of the threshold voltage of said field effect transistor.

Claim 19

The linear amplifier of claim 16, further comprising capacitive storage means operatively connected between the source and gate terminals of said field effect transistor.

Claim 20

In a linear amplification having an input terminal and an output terminal comprising a load device, a supply voltage and a semiconductor switching device having a control terminal and an output circuit, said output circuit of said switching device being operatively connected in series with said load device across said voltage supply, said control terminal being operatively connected to said input terminal, and said output terminal being operatively connected to the junction between said load device and said switching device, thE improvement comprising clocked feedback means for operatively connecting said output terminal and said input terminal during a first clock interval and effective to feed back a portion of said supply voltage to said input terminal during said first clock interval, said portion of said supply voltage being dependent upon the operating characteristics of said semiconductor switching device and the resistance of said load device, and to thereafter isolate said input terminal from said output terminal during a second clock interval, whereby said control terminal of said switching device is automatically self-biased to its linear amplification region.

Claim 21

In a linear amplification having an input terminal and an output terminal comprising a load device, a supply voltage and a semiconductor switching device having a control terminal and an output circuit, said output circuit of said switching device being operatively connected in series with said load device across said voltage supply, said control terminal being operatively connected to said input terminal, and said output terminal being operatively connected to the junction between said load device and said switching device, thE improvement comprising clocked feedback means for operatively connecting said output terminal and said input terminal during a first clock interval and effective to feed back a portion of said supply voltage to said input terminal during said first clock interval, said portion of said supply voltage being dependent upon the operating characteristics of said semiconductor switching device and the resistance of said load device, and to thereafter isolate said input terminal from said output terminal during a second clock interval, whereby said control terminal of said switching device is automatically self-biased to its linear amplification region.