Chopper stabilized amplifier

Claim 2

A chopper stabilized amplifier comprising, in combination: an amplifier input terminal; second and third terminals across which an input difference in potential may be applied; means for alternately connecting said second and third terminals to said amplifier input terminal during substantially mutually exclusive time intervals; an amplifier output terminal; first and second charge storage means; and means for connecting the first charge storage means to said output terminal and said second charge storage means to said input terminal during the times the second terminal is connected to said input terminal and for connecting the second charge storage means to said output terminal and said first storage means to said input terminal during the times the third terminal is connected to said amplifier input terminal.

Claim 3

In combination: an amplifier having an input terminal to which a signal to be amplified may be applied and an output terminal where the amplified signal is manifested; third and fourth terminals to which first and second signals, respectively, may be applied; means for connecting said third terminal to said input terminal during a first periodic time interval; means for connecting said fourth terminal to said input terminal during a second periodic time interval which is different from the first periodic time interval; and a pair of transmission paths connected between said input and output terminals, each of said paths including means for storing a portion of the amplified signal and means for transferring the stored signal to said input terminal, one of said transmission paths storing and the other one of said transmission paths transferring during said first periodic time interval, said transmission paths having the reverse operating roles during said second periodic time interval.

Claim 4

In combination: an amplifier having an input terminal to which a signal to be amplified may be applied and an output terminal where the amplified signal is manifested; third and fourth terminals to which first and second signals, respectively, may be applied; means for connecting said third terminal to said input terminal during a first periodic time interval; means for connecting said fourth terminal to said input terminal during a second periodic time interval which is different from the first periodic time interval; and a pair of transmission paths connected between said input and output terminals, each of said paths including means for storing a portion of the amplified signal and means for transferring the stored signal to said input terminal, one of said transmission paths storing and the other one of said transmission paths transferring during said first periodic time interval, said transmission paths having the reverse operating roles during said second periodic time interval.

Claim 5

The combination claimed in claim 2, including fifth and sixth terminals; and means for applying said amplified signal to said fifth terminal during said first periodic time interval and to said sixth terminal during said second periodic time interval.

Claim 6

In combination: an amplifier having an input terminal to which a signal to be amplified may be applied and an output terminal where the amplified signal is manifested; and first and second transmission paths connected between said input and output terminals, each of said first and second transmission paths including storage means for storing a portion of the amplified signal, said storage means in the first transmission path storing a signal in a first given time interval and said storage means in the second transmission path storing a signaL in a second given time interval different from the first given time interval, and each transmission path including transfer means for transferring its stored signal to said input terminal, said transfer means in the first path transferring during said second given time interval and said transfer means in the second path transferring during said first given time interval.

Claim 7

In combination: an amplifier having an input terminal to which a signal to be amplified may be applied and an output terminal where the amplified signal is manifested; and first and second transmission paths connected between said input and output terminals, each of said first and second transmission paths including storage means for storing a portion of the amplified signal, said storage means in the first transmission path storing a signal in a first given time interval and said storage means in the second transmission path storing a signaL in a second given time interval different from the first given time interval, and each transmission path including transfer means for transferring its stored signal to said input terminal, said transfer means in the first path transferring during said second given time interval and said transfer means in the second path transferring during said first given time interval.

Claim 8

In combination: means for chopping an input signal to produce a bilevel wave train; an amplifier receptive of said signal for producing an amplified version of said wave train; means for storing a first charge in response to each positive-going portion of the wave train; means for storing a second charge in response to each negative-going portion of the wave train; and means for feeding back to the input to said amplifier during the time it is producing the positive going portions of said wave train, the charge stored during the negative-going portions of the wave train and for feeding back to the input to said amplifier during the time it is producing the negative-going portions of the wave train, the charge stored during the positive-going portions of the wave train.

Claim 9

In combination: means for chopping an input signal to produce a bilevel wave train; an amplifier receptive of said signal for producing an amplified version of said wave train; means for storing a first charge in response to each positive-going portion of the wave train; means for storing a second charge in response to each negative-going portion of the wave train; and means for feeding back to the input to said amplifier during the time it is producing the positive going portions of said wave train, the charge stored during the negative-going portions of the wave train and for feeding back to the input to said amplifier during the time it is producing the negative-going portions of the wave train, the charge stored during the positive-going portions of the wave train.

Claim 10

In combination: an n-stage amplifier, where n is an integer, having an input terminal to which a signal to be amplified may be applied and an output terminal where the amplified signal is manifested; timing means for generating a first group of periodic timing signals phi 1 and a second group of periodic timing signals phi 2 which is essentially 180* out-of-phase with phi 1; first and second terminals to which first and second input signals may be applied, and means for connecting the first terminal to the input terminal of said amplifier in response to phi 1 and means for connecting the second terminal to the input terminal of said amplifier in response to phi 2; third and fourth terminals and means for connecting said third terminal to the output terminal of said amplifier in response to phi 1 and means for connecting said fourth terminal to the output terminal of said amplifier in response to phi 2; and first and second transmission paths connected between said input and output terminals, each including means for storing a portion of the amplified signal, said means in the first path storing the signal in response to phi 1 and said means in the second path storing the signal in response to phi 2, and each including means for transferring its stored signal to said input terminal, said means in the first path transferring in response to phi 2 and said means in the second path transferring in response to phi 2.

Claim 11

In combination: an n-stage amplifier, where n is an integer, having an input terminal to which a signal to be amplified may be applied and an output terminal where the amplified signal is manifested; timing means for generating a first group of periodic timing signals phi 1 and a second group of periodic timing signals phi 2 which is essentially 180* out-of-phase with phi 1; first and second terminals to which first and second input signals may be applied, and means for connecting the first terminal to the input terminal of said amplifier in response to phi 1 and means for connecting the second terminal to the input terminal of said amplifier in response to phi 2; third and fourth terminals and means for connecting said third terminal to the output terminal of said amplifier in response to phi 1 and means for connecting said fourth terminal to the output terminal of said amplifier in response to phi 2; and first and second transmission paths connected between said input and output terminals, each including means for storing a portion of the amplified signal, said means in the first path storing the signal in response to phi 1 and said means in the second path storing the signal in response to phi 2, and each including means for transferring its stored signal to said input terminal, said means in the first path transferring in response to phi 2 and said means in the second path transferring in response to phi 2.

Claim 12

In combination: an n-stage chopper stabilized amplifier, where n is an integer, having an input terminal to which a signal to be amplified may be applied and an output terminal at which the amplified signal is manifested; first and second terminals to which first and second signals may be applied; means for generating a first group of periodic timing signals phi 1; means for generating a second group of periodic timing signals phi 2 which is essentially 180* out-of-phase with phi 1; first and second transistors each having a source, drain, and gate electrode, the source electrode of the first being connected to the drain electrode of the second and to the input terminal of said amplifier, the drain electrode of the first being connected to said first terminal and the source electrode of the second being connected to said second terminal, the gate electrode of the first transistor being responsive to said first group of timing signals, and the gate electrode of the second being responsive to said second group of timing signals; third and fourth transistors each having a source, drain and gate electrode, the source electrode of the third being connected to the drain electrode of the fourth and to the output terminal of said amplifier, the gate electrode of the Third transistor being responsive to said first group of timing signals and the gate electrode of the fourth being responsive to said second group of timing signals; a third terminal connected to the drain electrode of the third transistor; a source of reference potential connected to the source electrode of the fourth transistor; fifth and sixth transistors each having a source and drain electrode, with a conduction path therebetween, and a gate electrode, the conduction paths of said fifth and sixth transistors being connected in series between the input and output terminals of said amplifier, the gate electrode of the fifth being responsive to said first group of timing signals and the gate electrode of the sixth being responsive to said second group of timing signals; and seventh and eighth transistors each having a source and drain electrode, with a conduction path therebetween, and a gate electrode, the conduction paths of said seventh and eighth transistors being connected in series between the input and output terminals of said amplifier, the gate electrode of the seventh being responsive to said first group of timing signals and the gate electrode of the sixth being responsive to said second group of timing signals.

Claim 13

In combination: an n-stage chopper stabilized amplifier, where n is an integer, having an input terminal to which a signal to be amplified may be applied and an output terminal at which the amplified signal is manifested; first and second terminals to which first and second signals may be applied; means for generating a first group of periodic timing signals phi 1; means for generating a second group of periodic timing signals phi 2 which is essentially 180* out-of-phase with phi 1; first and second transistors each having a source, drain, and gate electrode, the source electrode of the first being connected to the drain electrode of the second and to the input terminal of said amplifier, the drain electrode of the first being connected to said first terminal and the source electrode of the second being connected to said second terminal, the gate electrode of the first transistor being responsive to said first group of timing signals, and the gate electrode of the second being responsive to said second group of timing signals; third and fourth transistors each having a source, drain and gate electrode, the source electrode of the third being connected to the drain electrode of the fourth and to the output terminal of said amplifier, the gate electrode of the Third transistor being responsive to said first group of timing signals and the gate electrode of the fourth being responsive to said second group of timing signals; a third terminal connected to the drain electrode of the third transistor; a source of reference potential connected to the source electrode of the fourth transistor; fifth and sixth transistors each having a source and drain electrode, with a conduction path therebetween, and a gate electrode, the conduction paths of said fifth and sixth transistors being connected in series between the input and output terminals of said amplifier, the gate electrode of the fifth being responsive to said first group of timing signals and the gate electrode of the sixth being responsive to said second group of timing signals; and seventh and eighth transistors each having a source and drain electrode, with a conduction path therebetween, and a gate electrode, the conduction paths of said seventh and eighth transistors being connected in series between the input and output terminals of said amplifier, the gate electrode of the seventh being responsive to said first group of timing signals and the gate electrode of the sixth being responsive to said second group of timing signals.

Claim 14

In combination: amplifier means having an input terminal and an output terminal; first and second transmission paths connected from said output terminal to said input terminal; each of said transmission paths including storage means and transfer means; and control means connected to each of said transfer means for controlling the operation thereof such that each of said storage means selectively stores or supplies a signal representative of the signal at said output terminal to said input terminal.

Claim 15

In combination: amplifier means having an input terminal and an output terminal; first and second transmission paths connected from said output terminal to said input terminal; each of said transmission paths including storage means and transfer means; and control means connected to each of said transfer means for controlling the operation thereof such that each of said storage means selectively stores or supplies a signal representative of the signal at said output terminal to said input terminal.

Claim 16

The combination recited in claim 8 wherein said control means causes each of said transfer means to operate at different times such that the storage means of each of said transmission paths stores or supplies signals at different times, and each of said transfer means includes a semiconductor device.