US3836859A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Control circuit for preventing the response of a programmed controller to simultaneously generated control signals
Assignee: Siemens AG
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Filing: 1973-04-05
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Granted: 1974-09-17
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Expires: 1993-04-05
Abstract
Abstract A control circuit for preventing the response of a programmed controller to a plurality of simultaneously generated control signals, comprising a plurality of AND gates coupled to the signal generators of the controller; a monostable flip-flop means coupled to the outputs of the and gates for generating a first gate control signal whenever two or more control signals are generated simultaneously by the signal generators; and a bistable flip-flop means, coupled to the monostable flip-flop means, for generating a second gate control signal a predetermined time period after generation of the first gate control signal. The first and second gate control signals prevent the generation of output signals by the AND gates and the transmission of the signals to control signal storage devices in the controller.
Inventors
- 👤 D Behrens
- 👤 L Wache
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:32
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/048; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/085; G05B2219/00; G05B2219/20; G05B2219/23; G05B2219/23466
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
180 words
In a programmed controller including a plurality of control signal generators, a control circuit for preventing response by the controller to a plurality of control signals generated simultaneously thereby comprising: a. a plurality of logic gates each having an input coupled to a respective one of said plurality of control signal generators; b. first means coupled to the outputs of all of said gates for generating first gate control output signals for a predetermined time period whenever two or more control signals are generated simultaneously by the control signal generators; c. second means coupled to said first means for generating a second gate control output signal in response to a sequence of said first output signals; and d. means coupling said first and second gate control output signals as disabling inputs to all of said plurality of logic gates, whereby generation of output signals by said gate means in response to simultaneous control signals for a predetermined time period, and generation of said second output signal prevents generation thereof permanently, thereby preventing response to the controller to simultaneous control signals.
Claim 2
Dependent Claim
180 words
In a programmed controller including a plurality of control signal generators, a control circuit for preventing response by the controller to a plurality of control signals generated simultaneously thereby comprising: a. a plurality of logic gates each having an input coupled to a respective one of said plurality of control signal generators; b. first means coupled to the outputs of all of said gates for generating first gate control output signals for a predetermined time period whenever two or more control signals are generated simultaneously by the control signal generators; c. second means coupled to said first means for generating a second gate control output signal in response to a sequence of said first output signals; and d. means coupling said first and second gate control output signals as disabling inputs to all of said plurality of logic gates, whereby generation of output signals by said gate means in response to simultaneous control signals for a predetermined time period, and generation of said second output signal prevents generation thereof permanently, thereby preventing response to the controller to simultaneous control signals.
Claim 3
Dependent Claim
31 words
The control circuit as recited in claim 1 wherein said first means includes a monostable multivibrator having its output terminal coupled as said disabling input to all of said gate means.
Claim 4
Dependent Claim
47 words
The control circuit as recited in claim 2, wherein said first means further includes signal generating means for generating a flip-flop control output signal, and time delay means coupled to said signal generating means, for delaying transmission of said flip-flop control output signal to said monostable flip-flop.
Claim 5
Dependent Claim
43 words
The control circuit as recited in claim 3 wherein said time delay means delays transmission of said flip-flop control signal for a period of time which is one order of magnitude less than the duration of said first gate means control output signal.
Claim 6
Dependent Claim
55 words
The control circuit as recited in claim 1, wherein said second means comprises time delay means and a bistable flip-flop coupled thereto, said time delay means delaying transmission of said first gate means control output signal to said bistable flip-flop for a time period which is greater than the duration of said predetermined time period.
Claim 7
Dependent Claim
17 words
The control circuit as recited in claim 5, wherein said time delay means comprises an RC filter.
Claim 8
Dependent Claim
64 words
The control circuit as recited in claim 1 where each of said gate means comprises an AND gate having at least a non-inverting input and an inverting input and wherein the respective non-inverting inputs of said AND gates are coupled to said control signal generators and the inverting input terminals of all of said gates are coupled to said first and second output signals.
Claim 9
Dependent Claim
92 words
The control circuit as recited in claim 1 wherein said AND gates have at least two non-inverting inputs, one of which is coupled to respective ones of the control signal generators and further including an additional AND gate coupling said first and second output signals to a second non-inverting input of all of said plurality of AND gates, said additional AND gate being arranged to provide a disabling input to all of said plurality of AND gates in response to said first output signal and in response to said second output signal.
Claim 10
Dependent Claim
52 words
The control circuit as recited in claim 1, wherein the programmed controller also includes control signal storage means, coupled to said gate means, and time delay means, coupled to said storage means and said gate means, for delaying transmission of the control signals generated by said gate means to said storage means.
Claim 11
Dependent Claim
17 words
The control circuit as recited in claim 9 wherein said time delay means comprises an RC filter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-16 | 1978-03-18 | 1978-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-16 | 1982-03-18 | 1982-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-16 | 1986-03-18 | 1986-09-17 | $7700.00 | Window Closed / Lapsed |