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US3836722A Expired / Lapsed US ⏱️ 0.0 years remaining

Synchronizing method in time-division multiplex transmission systems

Assignee: Siemens AG
•
Filing: 1973-04-17
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Granted: 1974-09-17
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Expires: 1993-04-17
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Abstract

Abstract A method for synchronizing transmitting and receiving exchange stations is disclosed, wherein in unused portions of a time channel a channel number and accompanying designator are stored and transmitted. Upon receipt and detection of the designator, the channel number is compared in a comparator with the current value of a channel counter which designates storage locations in a receiver storage. If a mismatch is found a synchronizing unit is energized causing the next succeeding channel number to be loaded in the channel counter, establishing synchronization. As a safety measure, successive comparisons are carried out in the comparator to ensure that not a single isolated comparative match was established.

Inventors

  • 👤 H Muller
  • 👤 P Weidner

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 19:05
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 284 words
A synchronism method in time-division transmission system having a transmitter storage at the transmitter exchange and a receiver storage at the receiver exchange, wherein the transmission and reception of units of information take place under the control of a timing bit provided both to the transmitter exchange and at the receiver exchange, by which bit counters provided at the sending and at the receiving exchanges can be stepped, comprising: 1. generating a timing bit in the transmission system and providing said bit to said bit counters at the transmitting and receiving exchanges, 2. generating a channel pulse upon overflow of the bit counter at the receiver exchange, 3. applying the channel pulse to a word input register whose output is connected to said receiver storage and to a channel counter coupled to said receiver storage for determining the current storage location seized in said receiver storage, 4. transferring from said transmitter exchange to said receiver exchange in free positions of said determined channel the channel number and a designator of said channel number to said word input register, 5. transferring said received channel number to a comparator circuit for comparison with the curRent channel number produced by said channel counter in response to said channel pulse to determine if synchronism is maintained, and blocking the path of said word input register to said receiver storage if synchronism is not maintained, 6. displacing said bit sequence including the received timing bit by one channel position, 7. loading the next channel number received by said word input register and identified by its accompanying designator directly into said channel counter so that the storage location determined by said channel counter coincides with the presently seized storage location.
Claim 2
Dependent Claim 284 words
A synchronism method in time-division transmission system having a transmitter storage at the transmitter exchange and a receiver storage at the receiver exchange, wherein the transmission and reception of units of information take place under the control of a timing bit provided both to the transmitter exchange and at the receiver exchange, by which bit counters provided at the sending and at the receiving exchanges can be stepped, comprising: 1. generating a timing bit in the transmission system and providing said bit to said bit counters at the transmitting and receiving exchanges, 2. generating a channel pulse upon overflow of the bit counter at the receiver exchange, 3. applying the channel pulse to a word input register whose output is connected to said receiver storage and to a channel counter coupled to said receiver storage for determining the current storage location seized in said receiver storage, 4. transferring from said transmitter exchange to said receiver exchange in free positions of said determined channel the channel number and a designator of said channel number to said word input register, 5. transferring said received channel number to a comparator circuit for comparison with the curRent channel number produced by said channel counter in response to said channel pulse to determine if synchronism is maintained, and blocking the path of said word input register to said receiver storage if synchronism is not maintained, 6. displacing said bit sequence including the received timing bit by one channel position, 7. loading the next channel number received by said word input register and identified by its accompanying designator directly into said channel counter so that the storage location determined by said channel counter coincides with the presently seized storage location.
Claim 3
Dependent Claim 14 words
generating a channel pulse upon overflow of the bit counter at the receiver exchange,
Claim 4
Dependent Claim 14 words
generating a channel pulse upon overflow of the bit counter at the receiver exchange,
Claim 5
Dependent Claim 36 words
The method as set forth in claim 1, wherein said transferring and comparing step is repeated to establish multiple successive correspondence between said received channel numbers and said current channel number designated by said channel counter.
Claim 6
Dependent Claim 79 words
The method as set forth in claim 1 further comprising writing a predetermined bit comprising said designator into a location of the transmitter storage assigned to a time channel, cyclically reading each location of said transmitter storage until said designator is reached, blocking further information output from said transmitter storage upon reaching of said designator and transferring said channel number together with said designator from said transmitter storage to a word output register for transmission to the receiver exchange.
Claim 7
Dependent Claim 38 words
applying the channel pulse to a word input register whose output is connected to said receiver storage and to a channel counter coupled to said receiver storage for determining the current storage location seized in said receiver storage,
Claim 8
Dependent Claim 38 words
applying the channel pulse to a word input register whose output is connected to said receiver storage and to a channel counter coupled to said receiver storage for determining the current storage location seized in said receiver storage,
Claim 9
Dependent Claim 31 words
transferring from said transmitter exchange to said receiver exchange in free positions of said determined channel the channel number and a designator of said channel number to said word input register,
Claim 10
Dependent Claim 31 words
transferring from said transmitter exchange to said receiver exchange in free positions of said determined channel the channel number and a designator of said channel number to said word input register,
Claim 11
Dependent Claim 79 words
The method as set forth in claim 2 further comprising writing a predetermined bit comprising said designator into a location of the transmitter storage assigned to a time chanel, cyclically reading each location of said transmitter storage until said designator is reached, clocking further information output from said transmitter storage upon reaching of said designator and transferring said channel number together with said designator from said transmitter storage to a word output register for transmission to the receiver exchange.
Claim 12
Dependent Claim 30 words
A method as claimed in claim 3 wherein said designator is always stored in an unused bit position of said time channel in a bit location accompanying a channel number.
Claim 13
Dependent Claim 51 words
transferring said received channel number to a comparator circuit for comparison with the curRent channel number produced by said channel counter in response to said channel pulse to determine if synchronism is maintained, and blocking the path of said word input register to said receiver storage if synchronism is not maintained,
Claim 14
Dependent Claim 51 words
transferring said received channel number to a comparator circuit for comparison with the curRent channel number produced by said channel counter in response to said channel pulse to determine if synchronism is maintained, and blocking the path of said word input register to said receiver storage if synchronism is not maintained,
Claim 15
Dependent Claim 13 words
displacing said bit sequence including the received timing bit by one channel position,
Claim 16
Dependent Claim 13 words
displacing said bit sequence including the received timing bit by one channel position,
Claim 17
Dependent Claim 39 words
loading the next channel number received by said word input register and identified by its accompanying designator directly into said channel counter so that the storage location determined by said channel counter coincides with the presently seized storage location.
Claim 18
Dependent Claim 39 words
loading the next channel number received by said word input register and identified by its accompanying designator directly into said channel counter so that the storage location determined by said channel counter coincides with the presently seized storage location.

References Cited (Backward Citations)

US3742139A Cited
US3758722A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-09-16 1978-03-18 1978-09-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-09-16 1982-03-18 1982-09-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-09-16 1986-03-18 1986-09-17 $7700.00 Window Closed / Lapsed

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