Network for transposing signal bit interleaving patterns

Claim 2

In combination, a first shift register means having a number of stages at least equal to the number of pulse times in a time division multiplex signaL frame time wherein each said frame time includes a plurality of multipulse time slot signals and successive groups of said register means stages comprise time slot positions, a second shift register means, means for coupling signals between each time slot position of said first shift register means and said second shift register means in signal pulse parallel over a predetermined number, at least one, of said stages of each such time slot position, said number of said stages being less than the total number of stages of such time slot position.

Claim 3

The combination in accordance with claim 1 in which said first and second shift register means include means for operating such shift register means substantially continuously in a signal shifting mode at the same rate.

Claim 4

In combination, means for transmitting a time division multiplex signal including successive signal frames of plural time slot signals, each time slot signal including plural signal bits, means, operable at a predetermined signal bit rate, for presenting signal bits of corresponding bit positions in each time slot of a frame in a bit-parallel group comprising a miniframe of time division multiplex signals in which each time slot of said miniframe corresponds to a different time slot of one of said signal frames but includes only a part of the signal bits of such signal frame time slot, collector shift register means operable at said bit rate, means for transferring each bit-parallel group to said collector shift register means, and means for propagating signals from the collector shift register means to a common propagation circuit.

Claim 5

In combination, means for transmitting a time division multiplex signal including successive signal frames of plural time slot signals, each time slot signal including plural signal bits, means, operable at a predetermined signal bit rate, for presenting signal bits of corresponding bit positions in each time slot of a frame in a bit-parallel group comprising a miniframe of time division multiplex signals in which each time slot of said miniframe corresponds to a different time slot of one of said signal frames but includes only a part of the signal bits of such signal frame time slot, collector shift register means operable at said bit rate, means for transferring each bit-parallel group to said collector shift register means, and means for propagating signals from the collector shift register means to a common propagation circuit.

Claim 6

In combination, at least one time division multiplex signal highway, a plurality of first shift register means coupled to said highway, each shift register means having one stage per bit time of a time division multiplex signal transmission frame on said highway, signal transfer means coupled to plural predetermined stages of each of said shift register means, second shift register means each having a number of stages equal to the number of said signal transfer means for one of said first shift register means, each stage of the last-mentioned shift register means being coupled to a different one of said signal transfer means, and means, operative near the end of each signal transmission frame, for actuating said signal transfer means to transfer signals in a predetermined direction between said predetermined stages and said last-mentioned shift register means.

Claim 7

In combination, at least one time division multiplex signal highway, a plurality of first shift register means coupled to said highway, each shift register means having one stage per bit time of a time division multiplex signal transmission frame on said highway, signal transfer means coupled to plural predetermined stages of each of said shift register means, second shift register means each having a number of stages equal to the number of said signal transfer means for one of said first shift register means, each stage of the last-mentioned shift register means being coupled to a different one of said signal transfer means, and means, operative near the end of each signal transmission frame, for actuating said signal transfer means to transfer signals in a predetermined direction between said predetermined stages and said last-mentioned shift register means.

Claim 8

The combination in accordance with claim 4 in which each of said first shift register means comprises output coupling means in each of said predetermined stages thereof, said second shift register means stages each include input coupling means, and said signal transfer means comprise means for coupling each output coupling means to a different input coupling means of said second shift register means.

Claim 9

The combination in accordance with claim 4 in which each of said first shift register means comprises input coupling means in each of said predetermined stages thereof, said second shift register means stages each include output coupling means, and said signal transfer means comprise means for coupling each input coupling means to a different output coupling means of said second shift register means.

Claim 10

The combination in accordance with claim 4 in which said signal highway comprises means for coupling signals between said first shift register means and such highway at a first predetermined signal bit rate, and means are provided for actuating said first shift register means and said second shift register means in unison at a second predetermined signal bit rate that is different from said first rate by a factor which is equal to the product of the number of said first shift register means per highway times the number of time division signal bits that are simultaneously coupled from a highway to one of said first shift register means.

Claim 11

The combination in accordance with claim 4 in which signals on said time division multiplex signal highway comprise signal frames of a predetermined number of successive time slot signal bit groups in each frame, means are provided to couple a predetermined number, at least one, of bits at a time from said highway to each of said first shift register means, said shift register means and said signal transfer means comprise a substrate of material suitable for sustaining and propagating magnetic single wall domains, means overlayed on said substrate to enable for each of said first shift register means the propagation of magnetic single wall domain representations of signal bits through a serpentine path in which successive time slot word length signal byte positions each have a corresponding part, including a predetermined number of bit positions, aligned along a predetermined path, means, overlayed on said substrate, for enabling for said second shift register means the propagation of domains along a path parallel to said predetermined path, and means for coupling domains between said corresponding parts and respective stages of said second shift register means.

Claim 12

The combination in accordance with claim 8 in which said highway includes a plurality of circuits, one for each bit of a time slot, arranged for signal transmission in bit parallel, said circuits being grouped n circuits per group where n is equal to said predetermined number of bit positions, n means for controllably generating magnetic single wall domains at the first n input stages to each of said first shift register means, and means for coupling each said group of circuits to said generating means, respectively, for actuating such generating means in concert in response to signals on said circuits.

Claim 13

In combination, a first circuit means for propagating time division multiplex signals including signal transmission frames of plural time slot signals in which each time slot signal includes a plurality of signal bits, a second circuit means for transmitting time division multiplex signals including successive miniframes of time slot signals, each of which includes at least one signal bit, the total number of bits in each second circuit time slot being less than the total number of bits in each time slot on said first circuit, a plurality of frame shift registers, each register including a sufficient number of tandem-connected stages to contain a full frame of said time division signals of said first circuit means, a plurality of collector shift registers equal in number to the plurality of frame shift registers, each of said collector shift registers having a sufficient number of stages to accommodate in bit series at least one signal bit for each time slot of a frame of said first circuit means, means, operable at substantially the end of each of said first circuit means frames, for transferring signal representations in a predetermined direction between a frame register and the stages of a corresponding one of said collector shift registers, means for coupling said collector shift registers to provide signals to, or receive signals from, said second circuit means depending upon said predetermined direction of coupling in respect to the corresponding one of said frame shift registers, and means for coupling said first circuit means to provide signals to, or to receive signals from, each said frame register depending upon said predetermined direction of coupling in respect to the corresponding one of said frame shift registers.

Claim 14

In combination, a first circuit means for propagating time division multiplex signals including signal transmission frames of plural time slot signals in which each time slot signal includes a plurality of signal bits, a second circuit means for transmitting time division multiplex signals including successive miniframes of time slot signals, each of which includes at least one signal bit, the total number of bits in each second circuit time slot being less than the total number of bits in each time slot on said first circuit, a plurality of frame shift registers, each register including a sufficient number of tandem-connected stages to contain a full frame of said time division signals of said first circuit means, a plurality of collector shift registers equal in number to the plurality of frame shift registers, each of said collector shift registers having a sufficient number of stages to accommodate in bit series at least one signal bit for each time slot of a frame of said first circuit means, means, operable at substantially the end of each of said first circuit means frames, for transferring signal representations in a predetermined direction between a frame register and the stages of a corresponding one of said collector shift registers, means for coupling said collector shift registers to provide signals to, or receive signals from, said second circuit means depending upon said predetermined direction of coupling in respect to the corresponding one of said frame shift registers, and means for coupling said first circuit means to provide signals to, or to receive signals from, each said frame register depending upon said predetermined direction of coupling in respect to the corresponding one of said frame shift registers.

Claim 15

The combination in accordance with claim 10 in which each of said frame shift registers includes at least one input connection, said first circuit means comprises a plurality of circuit paths, each path transmitting at least one bit of each time slot signal on said first circuit means, means for coupling each of said paths To a different one of said frame shift register input connections, and means for coupling said collector shift registers in tandem for coupling said miniframe signals between said frame registers and said second circuit means.

Claim 16

The combination in accordance with claim 10 in which said first circuit means comprises a circuit for transmitting the bits of said frames in bit series, said first circuit coupling means comprises means for coupling each bit of a transmission frame to all of said frame registers, and further comprises delay propagation paths, having different amounts of delay, between said first circuit means and each of said frame registers, such that each bit enters each frame register in a different phase, and said means for coupling said collector registers to said second circuit means comprises, a shift register of (B-1) sections, each section including N stages of delay, where B equals the number of bits in a time slot of said transmission frame, and N equals the number of time slots in a transmission frame, and means for applying the output of each of said collector shift registers to said second circuit means through a different number of said B-1 sections, the numbers of sections being distributed among said collector registers inversely with respect to the amount of delay between said first circuit means and corresponding frame registers.

Claim 17

The combination in accordance with claim 10 in which said means for coupling said second circuit means to said collector registers comprises, a shift register of (B-1) sections, each section including N stages of delay, where B equals the number of bits in a time slot of said transmission frame, and N equals the number of time slots in a transmission frame, and means for applying miniframes from said second circuit means to each of said collector shift registers through a different number of said B-1 sections, said means for coupling said frame registers to said first circuit comprising OR logic means, and means for coupling each of said frame registers to a different input of said OR logic means through a different amount of signal propagation delay, said different amounts of signal propagation delay being distributed among said frame registers inversely with respect to the distribution of the numbers of said B-1 register sections.

Claim 18

The combination in accordance with claim 10 in which said first circuit means comprises input circuit means and output circuit means, said second circuit means comprises input circuit means, output circuit means, and signal utilization means coupled to receive signals from said output circuit means of said second circuit means and to supply signals to said input circuit means of said second circuit means, said plurality of frame shift registers include input frame registers coupled by said first circuit coupling means to receive signals from said first circuit input circuit means and include output frame registers coupled by said first circuit coupling means to provide signals to said first circuit output circuit means, and said plurality of collector shift registers include input collector registers coupled by said second circuit coupling means and said transferring means to couple signals from said input frame registers to said second circuit means output circuit means, and include output collector registers coupled by said second circuit coupling means and said transferring means to couple signals from said second circuit means input circuit means to said output frame registers.