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Patent US3835458A successfully refreshed from Google Patents.
US3835458A
Expired / Lapsed
US
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Die temperature controlled programming of ic memory device
Assignee: Individual
•
Filing: 1973-12-03
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Granted: 1974-09-10
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Expires: 1993-12-03
Abstract
Abstract The programming pulse rate of an integrated circuit memory array such as a voltage stressed programmable read only memory is controlled by sensing the temperature of the IC die. The memory device is rapidly pulsed until a preselected safe ceiling temperature is reached, and thereafter the rate of application of the pulses is controlled to maintain the temperature of the die at or near the safe ceiling temperature. The temperature of the die is sensed by measuring the voltage drop across a diode within the IC circuit, this voltage drop being a function of the temperature of the die, and the rate of pulsing of an oscillator, and thus the rate of application of the programming power pulses, is controlled in accordance with the diode voltage.
Inventors
- 👤 D Mrazek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:04
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; G11C16/00; G11C16/02; G11C16/06; G11C16/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
65 words
The method of programming an integrated circuit memory array with voltage stressing power pulses comprising the steps of producing a series of power pulses for application to the memory nodes of the memory array, sensing the temperature of the integrated circuit die, and controlling the rate of application of said power pulses to said integrated circuit in response to the level of said sensed temperature.
Claim 2
Independent Claim
65 words
The method of programming an integrated circuit memory array with voltage stressing power pulses comprising the steps of producing a series of power pulses for application to the memory nodes of the memory array, sensing the temperature of the integrated circuit die, and controlling the rate of application of said power pulses to said integrated circuit in response to the level of said sensed temperature.
Claim 3
Dependent Claim
34 words
The method as claimed in claim 1 wherein the step of sensing the temperature of the integrated circuit die comprises the step of sensing the voltage drop across a diode in said integrated circuit.
Claim 4
Dependent Claim
37 words
The method as claimed in claim 2 wherein said integrated circuit memory array is a programmable read only memory array and said diode is the phantom diode appearing across the bulk and source terminals of said circuit.
Claim 5
Dependent Claim
66 words
Apparatus for programming an integrated circuit memory array with voltage stressing power pulses comprising means for producing a series of power pulses for application to the memory nodes of the memory array, means for sensing the temperature of the integrated circuit die, and means responsive to the level of said sensed temperature for controlling the rate of application of said power pulses to said integrated circuit.
Claim 6
Dependent Claim
66 words
Apparatus for programming an integrated circuit memory array with voltage stressing power pulses comprising means for producing a series of power pulses for application to the memory nodes of the memory array, means for sensing the temperature of the integrated circuit die, and means responsive to the level of said sensed temperature for controlling the rate of application of said power pulses to said integrated circuit.
Claim 7
Dependent Claim
32 words
Apparatus as claimed in claim 4 wherein the means for sensing the temperature of the integrated circuit die comprises means for sensing the voltage drop across a diode in said integrated circuit.
Claim 8
Dependent Claim
36 words
Apparatus as claimed in claim 5 wherein said integrated circuit memory array is a programmable read only memory array and said diode is the phantom diode appearing across the bulk and source terminals of said circuit.
Claim 9
Dependent Claim
40 words
Apparatus as claimed in claim 4 wherein said means for producing a series of power pulses comprising a pulse generating oscillator circuit, said means for controlling the pulse rate comprising means for controlling the period of operation of said oscillator.
Claim 10
Dependent Claim
32 words
Apparatus as claimed in claim 7 wherein said means for sensing the temperature of the integrated circuit die comprises means for sensing the voltage drop across a diode in said integrated circuit.
Claim 11
Dependent Claim
37 words
The apparatus as claimed in claim 8 wherein said integrated circuit memory array in a programmable read only memory array and said diode is the phantom diode appearing across the bulk and source terminals of said circuit.
Claim 12
Dependent Claim
41 words
Apparatus as claimed in claim 9 wherein said means for controlling the rate of application of said power pulses comprises a sense amplifier have one input coupled to said bulk terminals and another input coupled to a source of reference voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-09 | 1978-03-11 | 1978-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-09 | 1982-03-11 | 1982-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-09 | 1986-03-11 | 1986-09-10 | $7700.00 | Window Closed / Lapsed |