Multiplexing connection between a key board and an integrated circuit device

Claim 2

A multiplexing connection arrangement for use between a keyboard and an integrated circuit device for entering individual key signals from the key switches of the keyboard into a storage register comprising a part of the integrated circuit device through a common multiplexed path requiring a minimal number of terminal connections to the integrated circuit device and utilizing timing signal generator means also included within the integrated circuit device for generating sets of individual timing signals and time boundary marker signals, the phases of which are sequentially shifted and do not overlap each other within specified intervals of time; said multiplexing connection arrangement comprising coupling circuit means coupled to the timing signal generator means and the key switches of the keyboard for coupling individual timing signals from the timing signal generator means through a common multiplexed path in response to the individual key signals from the key switches respectively at different points in time; counter means supplied by said coupling circuit means with the timing signals through a common multiplexed path; adder means coupled to said counter means and to said coupling circuit means for modifuing the count of the counter means in a predetermined code notation indicative of the encoded representation of respective operated keys in response to the timing signals and the individual key signals; and transfer means coupled to the counter means and to the timing signal generator means and responsive to the time boundary marker signals for transferring the contents of the counter means through a common multiplexed path into the storage register in the predetermined code notatioN.

Claim 3

A multiplexing connection arrangement for use between a keyboard and an integrated circuit device for entering individual key signals from the key switches of the keyboard into a storage register included within the integrated circuit device through a common multiplexed path and utilizing timing signal generator means comprising a part of the integrated circuit device for generating a train of individual timing signals including time boundary marker signals, the phases of which are sequentially shifted and do not overlap each other within specified intervals of time with the time boundary marker signals being indicative of the termination of a specified period of time; said multiplexing connection arrangement comprising coulpling circuit means coupled to the timing signal generator means and the individual key switches for coupling individual key signal coded timing signals from the timing signal generator means through a common multiplexed path in response to the individual key signals; counter means supplied by said coupling circuit means with the key signal encoded timing signals through the common multiplexed path; count modifying means coupled to said counter means and to said coupling circuit means for modifying the count of the counter means in a predetermined code notation in response to the key signal encoded timing signals, the operation of said counter means being carried out during a period of time between the initiation of a respective timing signal produced in response to the actuation of an operated key and the time boundary marker signal; and transfer means coupled to the counter means and the timing signal generator means and responsive to the time boundary marker signal for transferring the contents of the counter means through a common multiplexed path into the storage register in the predetermined code notation.

Claim 4

A multiplexing connection arrangement for use between a keyboard and an integrated circuit device for entering individual key signals from the key switches of the keyboard into a storage register included within the integrated circuit device through a common multiplexed path and utilizing timing signal generator means comprising a part of the integrated circuit device for generating a train of individual timing signals including time boundary marker signals, the phases of which are sequentially shifted and do not overlap each other within specified intervals of time with the time boundary marker signals being indicative of the termination of a specified period of time; said multiplexing connection arrangement comprising coulpling circuit means coupled to the timing signal generator means and the individual key switches for coupling individual key signal coded timing signals from the timing signal generator means through a common multiplexed path in response to the individual key signals; counter means supplied by said coupling circuit means with the key signal encoded timing signals through the common multiplexed path; count modifying means coupled to said counter means and to said coupling circuit means for modifying the count of the counter means in a predetermined code notation in response to the key signal encoded timing signals, the operation of said counter means being carried out during a period of time between the initiation of a respective timing signal produced in response to the actuation of an operated key and the time boundary marker signal; and transfer means coupled to the counter means and the timing signal generator means and responsive to the time boundary marker signal for transferring the contents of the counter means through a common multiplexed path into the storage register in the predetermined code notation.

Claim 5

A multiplexing connection arrangement according to claim 2, wherein the counter means comprises a multi-phase buffer storage for temporarily storing the results derived from the count modifying means and the count modifying means performs addition operations in synchronization with the timing signals.

Claim 6

A multiplexing connection arrangement according to claim 3, wherein the counter means further comprises gating means for enabling the addition operations during a period of time commencing with the timing signals initiated in response to the actuation of an operated key and terminating with the time boundary marker signal.

Claim 7

A multiplexing connection arrangement according to claim 4 wherein the count modifying means receives adder inputs during each period of the timing signals and then effects repeated additions in response to the inputs.

Claim 8

A multiplexing connection arrangement according to claim 5, wherein the count modifying means is of binary fashion type and the key signals via the common multiplexed path are directly translated into input information in the form of a plurality of binary bits, the number of which are dependent upon the differences in the points in time between the initiation of the key signal from the keyboard and the key time marker boundary signal.

Claim 9

A multiplexing connection arrangement according to claim 6 further comprising a flip flop for activating the gating means and which is set by the initiation of a key signal and reset by the time boundary marker signal.

Claim 10

A numeral input apparatus for entering a plurality of key signals from a keyboard into a storage register within an integrated circuit device through a common multiplexed path in selected sequence by translating them into multi-digit numeral information with each digit consisting of a plurality of binary bits, and with said keyboard comprising a plurality of key switches for providing numeral key signals; said input apparatus comprising timing signal generator means for generating separate sets of timing signals the phases of which are sequentially shifted and do not overlap each other within a specified period of time, said timing siGnal generator means including means for generating a time boundary marker signal indicative of the termination of the specified period of time; coupling means coupled to the timing signal generator means and the key switches for supplying only the individual set of timing signals associated with the actuation of a respective key switch and occurring at different points in time without overlap in time therebetween through a common multiplexing path; binary addition means coupled to the coupling circuit means and to said timing signal generator means and responsive to the timing signals for performing binary addition in response to each entered numeral key signal, during a period of time commencing at the initiation of a timing pulse produced in response to actuation of an operated key and terminating with the time boundary marker signal; counter means coupled to the binary addition means and responsive thereto for translating each numeral key signal into numerical information in the form of a single digit having a corresponding binary code representation consisting of a plurality of binary bits; and transfer means coupled to the counter means and to the timing signal generator means and responsive to the time boundary marker signal for transferring the results of the counter means indicative of the operated key into the storage register in the binary code decimal notation.

Claim 11

A numeral input apparatus for entering a plurality of key signals from a keyboard into a storage register within an integrated circuit device through a common multiplexed path in selected sequence by translating them into multi-digit numeral information with each digit consisting of a plurality of binary bits, and with said keyboard comprising a plurality of key switches for providing numeral key signals; said input apparatus comprising timing signal generator means for generating separate sets of timing signals the phases of which are sequentially shifted and do not overlap each other within a specified period of time, said timing siGnal generator means including means for generating a time boundary marker signal indicative of the termination of the specified period of time; coupling means coupled to the timing signal generator means and the key switches for supplying only the individual set of timing signals associated with the actuation of a respective key switch and occurring at different points in time without overlap in time therebetween through a common multiplexing path; binary addition means coupled to the coupling circuit means and to said timing signal generator means and responsive to the timing signals for performing binary addition in response to each entered numeral key signal, during a period of time commencing at the initiation of a timing pulse produced in response to actuation of an operated key and terminating with the time boundary marker signal; counter means coupled to the binary addition means and responsive thereto for translating each numeral key signal into numerical information in the form of a single digit having a corresponding binary code representation consisting of a plurality of binary bits; and transfer means coupled to the counter means and to the timing signal generator means and responsive to the time boundary marker signal for transferring the results of the counter means indicative of the operated key into the storage register in the binary code decimal notation.

Claim 12

A numeral input apparatus according to claim 8 wherein the addition performed by the addition means is inhibited when the key signals are indicative of numeral zero.

Claim 13

A functional information input apparatus for entering over a common multiplex path a plurality of key signals concerning the nature of arithmetic functions from a keyboard into a storage register within an integrated circuit device by translating the signals into functional information consisting of a plurality of binary bits having a corresponding binary code representation indicative of an operated key, said keyboard comprising a plurality of functional key switches for providing functional key signals representative of the actuation of respective functional key switches; said input apparatus comprising timing signal generator means for generating separate sets of timing signals the phases of which are sequentially shifted and do not overlap each other within a specified period of time and for further generating time boundary marker signals indicative of the termination of the specified period of time; coupling means coupled to the timing signal generator means and the key switches for intercoupling the individual sets of timing pulses with the functional key signals from the key switches respectively thereby to lead out the individual functional key signals at different points in time from the keyboard without overlap in time therebetween on a common multiplex path; binary addition means coupled to the coupling means and responsive to the timing signals for performing binary additions with each entered functional key signal, during a period of time commencing at the initiation of a timing signal associated with the actuation of an operated key and terminating with the boundary marker signal; counter means coupled to the binary addition means and responsive thereto for translating the functional key signal into information in the form of a single digit having corresponding binary code representation consisting of a plurality of binary bits; and transfer means coupled to the counter means and to the timing signal generator means and responsive to said time boundary marker signal for transferring the results of the binary addition means stored in said counter means into said storage register.

Claim 14

A functional information input apparatus for entering over a common multiplex path a plurality of key signals concerning the nature of arithmetic functions from a keyboard into a storage register within an integrated circuit device by translating the signals into functional information consisting of a plurality of binary bits having a corresponding binary code representation indicative of an operated key, said keyboard comprising a plurality of functional key switches for providing functional key signals representative of the actuation of respective functional key switches; said input apparatus comprising timing signal generator means for generating separate sets of timing signals the phases of which are sequentially shifted and do not overlap each other within a specified period of time and for further generating time boundary marker signals indicative of the termination of the specified period of time; coupling means coupled to the timing signal generator means and the key switches for intercoupling the individual sets of timing pulses with the functional key signals from the key switches respectively thereby to lead out the individual functional key signals at different points in time from the keyboard without overlap in time therebetween on a common multiplex path; binary addition means coupled to the coupling means and responsive to the timing signals for performing binary additions with each entered functional key signal, during a period of time commencing at the initiation of a timing signal associated with the actuation of an operated key and terminating with the boundary marker signal; counter means coupled to the binary addition means and responsive thereto for translating the functional key signal into information in the form of a single digit having corresponding binary code representation consisting of a plurality of binary bits; and transfer means coupled to the counter means and to the timing signal generator means and responsive to said time boundary marker signal for transferring the results of the binary addition means stored in said counter means into said storage register.

Claim 15

A multiplexing connection arrangement for use in connecting a keyboard and an integrated circuit device for entering individual key signals from the keyboard representative of desired numeral and functional information into a storage register through a common multiplexing path, the integrated circuit device including computation means for actIng on the numeral and functional information, the storage register being incorporated within the integrated circuit device for storing the key signals entered therein in a predetermined code notation, said integrated circuit device further including timing signal generator means for generating separate sets of timing signals and time boundary marker signals the phases of which are sequentially shifted and do not overlap each other within a specified period of time, and said keyboard comprising a plurality of key switches for providing individual key signals, the key switches being divided into a group of digit keys for entering numeral key signals and another group of function keys for entering functional key signals; said multiplexing connection arrangement comprising first coupling means coupled to the timing signal generator means and the group of digit key switches for coupling the individual timing signals with the key signals from the digit key switches respectively thereby to lead out individual sets of digit key signals at different points in time from the keyboard without overlap in time therebetween on a common multiplex path; second coupling means coupled to the timing signal generator means and the group of functional key switches respectively thereby to lead out individual sets of functional key signals at different points in time from the keyboard without overlap in time therebetween on the common path; detector means connected with the first and the second coupling means for determining whether the led out key signals are concerned with digit key signals or function key signals; counter means coupled to said first and second coupling means and responsive to the timing signals, adder means coupled to the counter means and to the first and second coupling means for modifying the count stored in the counter means in a predetermined code notation in response to the timing signals with the operation thereof being controlled by the led out digit and functional key signals; and transfer means responsive to said time boundary marker signals and said detector means for transferring the contents of the counter means indicative of the encoded representations of the operated digit and function keys into the storage register in the predetermined code notation.

Claim 16

A multiplexing connection arrangement for use in connecting a keyboard and an integrated circuit device for entering individual key signals from the keyboard representative of desired numeral and functional information into a storage register through a common multiplexing path, the integrated circuit device including computation means for actIng on the numeral and functional information, the storage register being incorporated within the integrated circuit device for storing the key signals entered therein in a predetermined code notation, said integrated circuit device further including timing signal generator means for generating separate sets of timing signals and time boundary marker signals the phases of which are sequentially shifted and do not overlap each other within a specified period of time, and said keyboard comprising a plurality of key switches for providing individual key signals, the key switches being divided into a group of digit keys for entering numeral key signals and another group of function keys for entering functional key signals; said multiplexing connection arrangement comprising first coupling means coupled to the timing signal generator means and the group of digit key switches for coupling the individual timing signals with the key signals from the digit key switches respectively thereby to lead out individual sets of digit key signals at different points in time from the keyboard without overlap in time therebetween on a common multiplex path; second coupling means coupled to the timing signal generator means and the group of functional key switches respectively thereby to lead out individual sets of functional key signals at different points in time from the keyboard without overlap in time therebetween on the common path; detector means connected with the first and the second coupling means for determining whether the led out key signals are concerned with digit key signals or function key signals; counter means coupled to said first and second coupling means and responsive to the timing signals, adder means coupled to the counter means and to the first and second coupling means for modifying the count stored in the counter means in a predetermined code notation in response to the timing signals with the operation thereof being controlled by the led out digit and functional key signals; and transfer means responsive to said time boundary marker signals and said detector means for transferring the contents of the counter means indicative of the encoded representations of the operated digit and function keys into the storage register in the predetermined code notation.

Claim 17

An electronic calculator comprising a keyboard having a plurality of key switches for entering key signals into the calculator; an integrated circuit device including a storage register for storing key signals entered therein said keyboard in a predetermined code notation and timing signal generator means for generating a train of timing signals the phases of which are sequentially shifted and do not overlap each other within a specified period of time; common coupling means coupled to the timing signal generator means within the integrated circuit device and to the key switches on the keyboard for coupling the individual timing signals in response to actuation of the key switches respectively thereby to lead out individual key signals at different points in time from the keyboard without overlap in time therebetween through a common multiplexed path; counter means coupled to said common coupling means; count modifying means coupled to said counter means and said common coupling means and responsive to the key signal encoded timing signals for modifying the stored count of said counter means in a predetermined code notation in response to the key signal encoded timing signals, the operation of the count modifying means being responsive to the key signal encoded timing signals led out in response to operated keys of the keyboard; transfer means coupled to the counter means and the timing signal generator means for transferring the contents of the counter means indicative of the encoded representation of the operated key into the storage register in the predetermined code notation; and display means coupled to the timing signal generator means and to the storage register for displaying the contents stored in the storaGe register.

Claim 18

An electronic calculator comprising a keyboard having a plurality of key switches for entering key signals into the calculator; an integrated circuit device including a storage register for storing key signals entered therein said keyboard in a predetermined code notation and timing signal generator means for generating a train of timing signals the phases of which are sequentially shifted and do not overlap each other within a specified period of time; common coupling means coupled to the timing signal generator means within the integrated circuit device and to the key switches on the keyboard for coupling the individual timing signals in response to actuation of the key switches respectively thereby to lead out individual key signals at different points in time from the keyboard without overlap in time therebetween through a common multiplexed path; counter means coupled to said common coupling means; count modifying means coupled to said counter means and said common coupling means and responsive to the key signal encoded timing signals for modifying the stored count of said counter means in a predetermined code notation in response to the key signal encoded timing signals, the operation of the count modifying means being responsive to the key signal encoded timing signals led out in response to operated keys of the keyboard; transfer means coupled to the counter means and the timing signal generator means for transferring the contents of the counter means indicative of the encoded representation of the operated key into the storage register in the predetermined code notation; and display means coupled to the timing signal generator means and to the storage register for displaying the contents stored in the storaGe register.

Claim 19

An electronic calculator according to claim 12 wherein the number of the timing pulses in each set of timing signals is less than the digit capacity of the storage register, said calculator further includes means for generating separation signals adapted to distinguish between digit key signals and function key signals in the storage register, and the individual key signals are led out at different points in time from the keyboard by utilizing combinations of the timing pulses and the separation signals.

Claim 20

In a multiplexing connection arrangement between a keyboard and an integrated circuit device for entering individual key signals from the keyboard into a storage register through a common multiplexed path, the storage register being incorporated within the integrated circuit device for storing the signals entered therein in a binary code notation; said multiplexing connection arrangement comprising means coupled to the keyboard for deriving individual key signals led out from the keyboard at different points in time with the use of separate sets of timing signals and time boundary marker signals the phases of which are sequentially shifted and do not overlap each other within a specified period of time; common multi-stage counter means coupled to the coupling means; adder means coupled to the counter means and to the coupling means for modifying the count stored in the counter means in binary notation in response to the individual key signal encoded timing signals supplied to the counter means by said coupling means; and transfer means coupled to the counter means and responsive to the time boundary marker signal for transferring the contents of the counter means indicative of the binary encoded representation of a respective operated key as input information in the form of a plurality of binary bits into the storage register.

Claim 21

In a multiplexing connection arrangement between a keyboard and an integrated circuit device for entering individual key signals from the keyboard into a storage register through a common multiplexed path, the storage register being incorporated within the integrated circuit device for storing the signals entered therein in a binary code notation; said multiplexing connection arrangement comprising means coupled to the keyboard for deriving individual key signals led out from the keyboard at different points in time with the use of separate sets of timing signals and time boundary marker signals the phases of which are sequentially shifted and do not overlap each other within a specified period of time; common multi-stage counter means coupled to the coupling means; adder means coupled to the counter means and to the coupling means for modifying the count stored in the counter means in binary notation in response to the individual key signal encoded timing signals supplied to the counter means by said coupling means; and transfer means coupled to the counter means and responsive to the time boundary marker signal for transferring the contents of the counter means indicative of the binary encoded representation of a respective operated key as input information in the form of a plurality of binary bits into the storage register.