Patent US3833930A successfully refreshed from Google Patents.
US3833930A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input/output system for a microprogram digital computer
Assignee: Unisys Corp
•
Filing: 1973-01-12
•
Granted: 1974-09-03
•
Expires: 1993-01-12
Abstract
Abstract An input/output sub-system for a digital data processing system having a microprogrammed processor and main memory in which the processor functions as a multiplexor for transferring data between a plurality of peripheral devices and the memory. The I/O controls for the peripheral devices share a common bus to the processor. The controls are slaved to the processor and operate to send or receive information over the common bus only in response to commands from the processor. However, any I/O control unit can signal the processor that it needs service. Each command addressed to one of the I/O control units is followed by status information returned on the bus to the processor by the I/O control. In addition, the status of an I/O control can be tested on special command from the processor. Each I/O control is buffered for storage of a block of data. A reference address pointing to the location of the Input/Output Descriptor in memory being executed by the processor is transferred to the control and stored in the buffer. It is returned to the processor after a Service Request by the control is acknowledged by the processor.
Inventors
- 👤 J Macker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:01
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/122
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
408 words
A data processing system comprising a memory; a microprogrammed processor including a plurality of registers, a main data bus having a plurality of parallel lines interconnecting the registers with each other and with memory, and control means including a control register for storing a micro-operator and a control bus connected to the control register for controlling transfer of data over said data bus among selected register and memory; an input/output bus having A plurality of parallel lines; a plurality of input/output control units connected to said input/output bus, each control unit being connected to at least one input/output device; and interface means connecting the input/output bus to the data bus, said interface means including means connected to the control bus and responsive to a first predetermined micro-operator in the control register of the processor for coupling a group of data bits in parallel from one of said registers designated by the microoperator over the data bus to the input/output bus, means responsive to said first micro-operator for applying a first control signal to each of the input/output control units to signal the control units that data is on the input/output bus, means responsive to a second predetermined micro-operator in the control register of the processor for coupling a group of data bits in parallel over the input/output bus to the data bus and to one of said registers designated by the micro-operator, and means responsive to said second micro-operator for applying a second control signal to each of the control units to signal the control units that data is on the data bus; each control unit including a command register, means responsive to said first control signal for loading the command register in the associated control unit with data bits on a first group of the said parallel lines of the input/output bus, address decoding means responsive to said first control signal from the interface means for generating a channelactive signal in the associated control unit when designated by the coded conditions of data bits on a second group of said parallel lines of the input-output bus, a status register having a plurality of states, each state of the status register defining a control state of the control unit, means responsive to said second control signal from the interface means and the channelactive signal when both signals are present in the control unit for applying the state of the status register in coded form onto the input/output bus.
Claim 2
Dependent Claim
408 words
A data processing system comprising a memory; a microprogrammed processor including a plurality of registers, a main data bus having a plurality of parallel lines interconnecting the registers with each other and with memory, and control means including a control register for storing a micro-operator and a control bus connected to the control register for controlling transfer of data over said data bus among selected register and memory; an input/output bus having A plurality of parallel lines; a plurality of input/output control units connected to said input/output bus, each control unit being connected to at least one input/output device; and interface means connecting the input/output bus to the data bus, said interface means including means connected to the control bus and responsive to a first predetermined micro-operator in the control register of the processor for coupling a group of data bits in parallel from one of said registers designated by the microoperator over the data bus to the input/output bus, means responsive to said first micro-operator for applying a first control signal to each of the input/output control units to signal the control units that data is on the input/output bus, means responsive to a second predetermined micro-operator in the control register of the processor for coupling a group of data bits in parallel over the input/output bus to the data bus and to one of said registers designated by the micro-operator, and means responsive to said second micro-operator for applying a second control signal to each of the control units to signal the control units that data is on the data bus; each control unit including a command register, means responsive to said first control signal for loading the command register in the associated control unit with data bits on a first group of the said parallel lines of the input/output bus, address decoding means responsive to said first control signal from the interface means for generating a channelactive signal in the associated control unit when designated by the coded conditions of data bits on a second group of said parallel lines of the input-output bus, a status register having a plurality of states, each state of the status register defining a control state of the control unit, means responsive to said second control signal from the interface means and the channelactive signal when both signals are present in the control unit for applying the state of the status register in coded form onto the input/output bus.
Claim 3
Dependent Claim
70 words
Apparatus of claim 1 wherein each input/output control unit further comprises a buffer memory, and means responsive to the simultaneous presence of said first control signal from the interface means, the channel-active signal, and a predetermined condition of the data bits on said first group of lines of the input/output bus for transferring the data bits on a third group of lines of the input/output bus to the buffer memory.
Claim 4
Dependent Claim
58 words
Apparatus of claim 1 wherein each input/output control unit further comprises a buffer memory, and means responsive to the presence of said second control signal from the interface means and a first predetermined condition of said command register for transferring a group of data bits from the buffer register to a group of lines of the input/output bus.
Claim 5
Dependent Claim
72 words
Apparatus of claim 1 wherein each control unit further includes means for generating a service request signal when service of the unit by the processor is required, and means responsive to a second predetermined condition of said command register and the presence of the service request signal for transferring a bit on a predetermined one of the lines of the input/output bus, each control unit utilizing a different one of said lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-02 | 1978-03-04 | 1978-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-02 | 1982-03-04 | 1982-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-02 | 1986-03-04 | 1986-09-03 | $7700.00 | Window Closed / Lapsed |