Apparatus for detecting data bits and error bits in phase encoded data

Claim 2

Apparatus for detecting data bits and error bits in phase encoded data, for use with a source of data, a source of timing pulses, a source of enable signals and a source of preamble end signals, said apparatus comprising: first, second, third and fourth flip-flops each having first, second and third input leads and first and second output leads, said second input lead of said first flip-flop being coupled to said source of pulses, said first and said third input leads of said second and said third flip-flops each being coupled to said source of data, said first input lead of said fourth flipflop being coupled to said source of said enable signals, said first output lead of said first flip-flop being coupled to said second input lead of said second and said fourth flip-flops, said second output lead of said first flip-flop being coupled to said second input lead of said third flip-flop; first and second reference potentials, said first potential being connected to said first and said third input leads of said first flip-flop, said second potential being connected to said third input lead of said fourth flip-flop; first and second Logic gates each having first, second and third input leads and an output lead, said first, second and third input leads of said first gate being connected to a corresponding one of said first output leads of said second, third and fourth flip-flops, said first input lead of said second gate being connected to said first output lead of said fourth flip-flop, said second input lead of said second gate being connected to said second output lead of said second flip-flop, said third input lead of said second gate being connected to said second output lead of said third flip-flop; first gating means for providing an error signal when one of said first and said second logic gates is enabled, said first gating means being coupled to said output lead of first logic gate, to said output lead of second logic gate and to said first output lead of said first flip-flop.

Claim 3

Apparatus for detecting data bits and error bits in phase encoded data, for use with a source of data and a source of timing pulses, said apparatus comprising: first and third flip-flops each having first, second and third input leads and an output lead, said second input lead of said first flip-flop being connected to said source of pulses, said first and said third input leads of said third flip-flop being coupled to said source of data, said second input lead of said third flip-flop being coupled to said lead of said first flip-flop; a gating means, said gating means being coupled to said output lead of said first flip-flop and to said output lead of said third flip-flop; and a first reference potential, said first potential being coupled to said first and said third input leads of said first flip-flop.

Claim 4

Apparatus for detecting data bits and error bits in phase encoded data, for use with a source of data and a source of timing pulses, said apparatus comprising: first and third flip-flops each having first, second and third input leads and an output lead, said second input lead of said first flip-flop being connected to said source of pulses, said first and said third input leads of said third flip-flop being coupled to said source of data, said second input lead of said third flip-flop being coupled to said lead of said first flip-flop; a gating means, said gating means being coupled to said output lead of said first flip-flop and to said output lead of said third flip-flop; and a first reference potential, said first potential being coupled to said first and said third input leads of said first flip-flop.

Claim 5

Apparatus for detecting data bits and error bits in phase encoded data, for use with a source of data, a source of timing pulses and a source of enable signals, said apparatus comprising: first, third, fourth and fifth flip-flops each having first, second and third input leads and first and second output leads, said second input lead of said first flip-flop being connected to said source of pulses, said first and said third input leads of said third flip-flop being coupled to said source of data, said second input leads of said fourth and fifth flip-flops being coupled to said first output lead of said first flip-flop, said second input lead of said third flip-flop being coupled to said second output lead of said first flip-flop; first and second reference potentials, said first reference potential being connected to said first and said third input leads of said first flip-flop, said second reference potential being connected to said third input lead of said fourth and said fifth flip-flops, said first input lead of said fourth flip-flop being coupled to said source of enable signals, said first output lead of said fourth flip-flop being coupled to said first input lead of said fifth flip-flop; and a gating means, said gating means being coupled to said first output lead of said third and said fifth flip-flops.

Claim 6

Apparatus for detecting data bits and error bits in phase encoded data, for use with a source of data, a source of timing pulses and a source of enable signals, said apparatus comprising: first, third, fourth and fifth flip-flops each having first, second and third input leads and first and second output leads, said second input lead of said first flip-flop being connected to said source of pulses, said first and said third input leads of said third flip-flop being coupled to said source of data, said second input leads of said fourth and fifth flip-flops being coupled to said first output lead of said first flip-flop, said second input lead of said third flip-flop being coupled to said second output lead of said first flip-flop; first and second reference potentials, said first reference potential being connected to said first and said third input leads of said first flip-flop, said second reference potential being connected to said third input lead of said fourth and said fifth flip-flops, said first input lead of said fourth flip-flop being coupled to said source of enable signals, said first output lead of said fourth flip-flop being coupled to said first input lead of said fifth flip-flop; and a gating means, said gating means being coupled to said first output lead of said third and said fifth flip-flops.

Claim 7

Apparatus for detecting data bits and error bits in phase encoded data, for use with a source of timing pulses, a source of enable signals and a source of preamble end signals, said apparatus comprising: first, fourth and sixth flip-flops each having first, second and third input leads and first and second output leads, said second input lead of said first flip-flop being connected to said source of pulses, said first input lead of said fourth flip-flop being connected to said source of enable signals, said second input lead of said fourth and said sixth flip-flops being coupled to said first output lead of said first flip-flop; first and second reference potentials, said first potential being coupled to said first and said third input leads of said first flip-flop, said second potential being connected to said third input lead of said fourth and said sixth flip-flops; a logic gate having first and second input leads and an output lead, saId first input lead of said logic gate being coupled to said second output lead of said fourth flip-flop, said second input lead of said logic gate being coupled to said source of preamble end signals, said output lead of said logic gate being coupled to said first input lead of said sixth flip-flop; and an output terminal, said output terminal being connected to said second output lead of said sixth flip-flop.

Claim 8

Apparatus for detecting data bits and error bits in phase encoded data, for use with a source of timing pulses, a source of enable signals and a source of preamble end signals, said apparatus comprising: first, fourth and sixth flip-flops each having first, second and third input leads and first and second output leads, said second input lead of said first flip-flop being connected to said source of pulses, said first input lead of said fourth flip-flop being connected to said source of enable signals, said second input lead of said fourth and said sixth flip-flops being coupled to said first output lead of said first flip-flop; first and second reference potentials, said first potential being coupled to said first and said third input leads of said first flip-flop, said second potential being connected to said third input lead of said fourth and said sixth flip-flops; a logic gate having first and second input leads and an output lead, saId first input lead of said logic gate being coupled to said second output lead of said fourth flip-flop, said second input lead of said logic gate being coupled to said source of preamble end signals, said output lead of said logic gate being coupled to said first input lead of said sixth flip-flop; and an output terminal, said output terminal being connected to said second output lead of said sixth flip-flop.

Claim 9

Apparatus for detecting data bits and error bits in phase encoded data, for use with a source of data, a source of timing pulses, a source of enable signals, a source of preamble end signals, and a source of fast envelope detect signals, said apparatus comprising: first, fourth, fifth and sixth flip-flops each having first, second and third input leads, a set lead and first and second output leads, said second input lead of said first flip-flop being coupled to said source of pulses, said second input lead of said fourth, said fifth and said sixth flip-flops each being coupled to said first output lead of said first flip-flop, said first input lead of said fourth flip-flop being coupled to said source of enable signals, said first input lead of said fifth flip-flop being coupled to said first output lead of said fourth flip-flop, first and second reference potentials, said first potential being connected to said first and said third input leads of said first flip-flop, said second potential being connected to said third input leads of said fourth, said fifth and said sixth flip-flops; a first gating means having first and second input leads and an output lead, said first input lead of said first gating means being connected to said source of fast envelope detect signals, said second input lead of said first gating means being coupled to said first output lead of said fifth flip-flop, said output lead of said first gating means being coupled to said set input lead of said sixth flip-flop; and an output terminal, said output terminal being connected to said second output lead of said sixth flip-flop.

Claim 10

Apparatus for detecting data bits and error bits in phase encoded data, for use with a source of data, a source of timing pulses, a source of enable signals, a source of preamble end signals, and a source of fast envelope detect signals, said apparatus comprising: first, fourth, fifth and sixth flip-flops each having first, second and third input leads, a set lead and first and second output leads, said second input lead of said first flip-flop being coupled to said source of pulses, said second input lead of said fourth, said fifth and said sixth flip-flops each being coupled to said first output lead of said first flip-flop, said first input lead of said fourth flip-flop being coupled to said source of enable signals, said first input lead of said fifth flip-flop being coupled to said first output lead of said fourth flip-flop, first and second reference potentials, said first potential being connected to said first and said third input leads of said first flip-flop, said second potential being connected to said third input leads of said fourth, said fifth and said sixth flip-flops; a first gating means having first and second input leads and an output lead, said first input lead of said first gating means being connected to said source of fast envelope detect signals, said second input lead of said first gating means being coupled to said first output lead of said fifth flip-flop, said output lead of said first gating means being coupled to said set input lead of said sixth flip-flop; and an output terminal, said output terminal being connected to said second output lead of said sixth flip-flop.

Claim 11

Apparatus for detecting data bits and error bits in phase encoded data as defined in claim 5 including: a second gating means having first and second input leads and an output lead, said first input lead of said second logic gate being connected to said second output lead of said fourth flip-flop, said second input lead of said second gating means being coupled to said source of preamble end signals, said output lead of said second gating means being coupled to said first input lead of said sixth flip-flop.

Claim 12

Apparatus for detecting data bits and error bits in phase encoded data, for use with a source of data, a source of timing pulses, a source of enable signals, a source of preamble end signals, and a source of fast envelope detect signals, said apparatus comprising: first, second, third, fourth, fifth, and sixth flip-flops each having first, second, third and set input leads and first and second output leads, said second input lead of said first flip-flop being connected to said source of timing pulses, said first output lead of said first flip-flop being connected to said second input lead of said second, said fourth, said fifth and said sixth flip-flops, said second output lead of said first flip-flop being connected to said second input lead of said first flip-flop being connected to said second input lead of said third flip-flop, said first and said third input leads of said second and said third flip-flops each being coupled to said source of data, said first input lead of said fourth flip-flop being coupled to said source of enable signals; first, second and third logic gates each having first, second and third input leads and an output lead, said input leads of said first logic gate each being coupled to a corresponding one of said first output leads of said second, said third and said fourth flip-flops, said first and said second input leads of said second logic gate each being connected to a corresponding oNe of said second output leads of said second and said third flip-flops, said third input lead of said second logic gate being connected to said first output lead of said fourth flip-flop, said output lead of said first logic gate being connected to said first input lead of said third logic gate, said output lead of said second logic gate being connected to said second input lead of said third logic gate, said second output lead of said sixth flip-flop being connected to said third input lead of said third logic gate; first and second reference potentials, said first potential being connected to said first and said third input leads of said first flip-flop, each second potential being connected to said third input lead of said fourth said fifth and said sixth flip-flops; first gating means having first and second input leads and an output lead, said first input lead of said first gating means being connected to said output lead of said third logic gate, said second input lead of said first gating means being coupled to said second output lead of said fifth flip-flop, said output lead of said logic means being coupled to said first input lead of said sixth flip-flop, said first input lead of said fifth flip-flop being coupled to said first output lead of said fourth flip-flop; and an output terminal, said output terminal being connected to said second output lead of said sixth flip-flop.

Claim 13

Apparatus for detecting data bits and error bits in phase encoded data, for use with a source of data, a source of timing pulses, a source of enable signals, a source of preamble end signals, and a source of fast envelope detect signals, said apparatus comprising: first, second, third, fourth, fifth, and sixth flip-flops each having first, second, third and set input leads and first and second output leads, said second input lead of said first flip-flop being connected to said source of timing pulses, said first output lead of said first flip-flop being connected to said second input lead of said second, said fourth, said fifth and said sixth flip-flops, said second output lead of said first flip-flop being connected to said second input lead of said first flip-flop being connected to said second input lead of said third flip-flop, said first and said third input leads of said second and said third flip-flops each being coupled to said source of data, said first input lead of said fourth flip-flop being coupled to said source of enable signals; first, second and third logic gates each having first, second and third input leads and an output lead, said input leads of said first logic gate each being coupled to a corresponding one of said first output leads of said second, said third and said fourth flip-flops, said first and said second input leads of said second logic gate each being connected to a corresponding oNe of said second output leads of said second and said third flip-flops, said third input lead of said second logic gate being connected to said first output lead of said fourth flip-flop, said output lead of said first logic gate being connected to said first input lead of said third logic gate, said output lead of said second logic gate being connected to said second input lead of said third logic gate, said second output lead of said sixth flip-flop being connected to said third input lead of said third logic gate; first and second reference potentials, said first potential being connected to said first and said third input leads of said first flip-flop, each second potential being connected to said third input lead of said fourth said fifth and said sixth flip-flops; first gating means having first and second input leads and an output lead, said first input lead of said first gating means being connected to said output lead of said third logic gate, said second input lead of said first gating means being coupled to said second output lead of said fifth flip-flop, said output lead of said logic means being coupled to said first input lead of said sixth flip-flop, said first input lead of said fifth flip-flop being coupled to said first output lead of said fourth flip-flop; and an output terminal, said output terminal being connected to said second output lead of said sixth flip-flop.

Claim 14

Apparatus for detecting data bits and error bits in phase encoded data as defined in claim 7 including: a second gating means having first and second input leads and an output lead, said first input lead of said second gating means being coupled to said source of fast envelope detect signals, said second input lead of said second gating means being connected to said first output lead of said fifth flip-flop, said output lead of said second gating means being connected to said set input lead of said sixth flip-flop.

Claim 15

Apparatus for detecting data bits and error bits in phase encoded data as defined in claim 7 including: a third gating means having first and second input leads and an output lead, said first input lead of said third gating means being connected to said second output lead of said fourth flip-flop, said second input lead of said third gating means being coupled to said source of preamble end signals, said output lead of said third gating means being coupled to said first input lead of said sixth flip-flop.

Claim 16

Apparatus for detecting data bits and error bits in phase encoded data as defined in claim 7 including: second and third gating means each having first and second input leads and an output lead, said first input lead of said second gating means being coupled to said source of fast envelope detect signals, said second input lead of said second gating means being connected to said first output lead of said fifth flip-flop, said output lead of said second gating means being connected to said set input lead of said sixth flip-flop, said first input lead of said third gating means being connected to said second output lead of said fourth flip-flop, said second input lead of said third gating means being coupled to said source of preamble end signals, said output lead of said third gating means being coupled to said first input lead of said sixth flip-flop.

Claim 17

Apparatus for detecting data bits and error bits in phase encoded data as defined in claim 7 including: second and third gating means each having first and second input leads and an output lead, said first input lead of said second gating means being coupled to said source of fast envelope detect signals, said second input lead of said second gating means being connected to said first output lead of said fifth flip-flop, said output lead of said second gating means being connected to said set input lead of said sixth flip-flop, said first input lead of said third gating means being connected to said second output lead of said fourth flip-flop, said second input lead Of said third gating means being coupled to said source of preamble end signals, said output lead of said third gating means being coupled to said first input lead of said sixth flip-flop; a fourth logic gate having first, second and third input leads and an output lead, said first input lead of said fourth logic gate being coupled to said first output lead of said first flip-flop, said second input lead of said fourth logic gate being connected to said output lead of said third logic gate, said third input lead of said fourth logic gate being connected to said second output lead of said sixth flip-flop; and a second output terminal, said second terminal being connected to said output lead of said fourth gating means.