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US3828344A Expired / Lapsed US ⏱️ 0.0 years remaining

Double density to nrz code converter

Assignee: Dyncorp Information Systems LLC
•
Filing: 1973-01-02
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Granted: 1974-08-06
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Expires: 1993-01-02
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Abstract

Abstract A data converting apparatus for converting double density encoded signals to NRZ (non-return-to-zero) encoded signals. A double density encoded signal is gated into a first flip-flop by a first train of clock pulses and also into a second flip-flop by a second train of clock pulses phase displaced with respect to the first train of clock pulses. For each transition in the double density encoded signal from a first level to a second level, for example, from a low level to a high level, a first AND gate coupled to the two flip-flops produces an output pulse. For each transition in the double density encoded signal from the second level to the first level, that is, from the high level to the low level, a second AND gate coupled to the two flip-flops produces an output pulse. The output pulses produced by the two AND gates are inverted and combined by a NOR gate into a single pulse train and applied to a third flip-flop together with the second train of clock pulses. The pulse train applied by the NOR gate to the third flip-flop is delayed by a slight amount with respect to the second train of clock pulses due to propagation delays inherent in the data converting apparatus due to the presence of the first and second flip-flops, the AND gates, and the NOR gate. The third flip-flop operates to sample the levels of the single pulse train received from the NOR gate at the times of occurrence of the leading edges of successive clock pulses in the second train of clock pulses. Each time that the pulse train received from the NOR gate is low at the time of occurrence of the leading edge of a clock pulse in the second train of clock pulses, the third flip-flop assumes a first state, for example a ''''1'''' state. Each time that the pulse train received from the NOR gate is high at the time of occurrence of the leading edge of a clock pulse in the second train of clock pulses, the third flip-flop assumes a second state, for example, a ''''0'''' state. The switching of the third flip-flop between its two states is determined by the levels of the pulse train received from the NOR gate at the times of occurrence of the leading edges of successive clock pulses in the second train of clock pulses.

Inventors

  • 👤 W Schwartz
  • 👤 R Butler

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 17:26
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 407 words
A data converting apparatus for converting a double density encoded signal into an NRZ encoded signal, said double density encoded signal comprising successive bit periods and including transitions between first and second levels, said data converting apparatus comprising: first means having first and second output connections and adapted to receive a double density encoded signal and first and second trains of pulses, said first and second trains of pulses comprising pulses each having a width equal to a fraction of a bit period of the double density encoded signal and said second train of pulses being phase displaced with respect to the first train of pulses by said fraction of a bit period, said first means being operative in response to the double density encoded signal and the first and second trains of pulses to produce an output signal at its first output connection for each transition in the double density encoded signal from the first level to the second level and to produce an output signal at its second output connection for each transition in the double density encoded signal from the second level to the first level; second means coupled to the first and second output connections of the first means and having an output connection said second means being operative to combine the output signals produced at the first and second output connections of the first means into a single signal at its output connection, said single signal including signals corresponding to the output signals produced at the first and second output connections of the first means; delay means operative to cause the signal produced by the second means to be delayed with respect to the second train of pulses by an amount less than the aforesaid fraction of a bit period; and third means adapted to receive the delayed signal and the second train of pulses, said third means being operative to sample the levels of the delayed signal at the times of occurrence of predetermined transitions of the second train of pulses and to produce an output having a first value each time that the delayed signal is at a first level at the time of occurrence of an aforesaid transition in the second train of pulses and to produce an output having a second value each time that the delayed signal is at a second level at the time of occurrence of an aforesaid transition in the second train of pulses.
Claim 2
Dependent Claim 407 words
A data converting apparatus for converting a double density encoded signal into an NRZ encoded signal, said double density encoded signal comprising successive bit periods and including transitions between first and second levels, said data converting apparatus comprising: first means having first and second output connections and adapted to receive a double density encoded signal and first and second trains of pulses, said first and second trains of pulses comprising pulses each having a width equal to a fraction of a bit period of the double density encoded signal and said second train of pulses being phase displaced with respect to the first train of pulses by said fraction of a bit period, said first means being operative in response to the double density encoded signal and the first and second trains of pulses to produce an output signal at its first output connection for each transition in the double density encoded signal from the first level to the second level and to produce an output signal at its second output connection for each transition in the double density encoded signal from the second level to the first level; second means coupled to the first and second output connections of the first means and having an output connection said second means being operative to combine the output signals produced at the first and second output connections of the first means into a single signal at its output connection, said single signal including signals corresponding to the output signals produced at the first and second output connections of the first means; delay means operative to cause the signal produced by the second means to be delayed with respect to the second train of pulses by an amount less than the aforesaid fraction of a bit period; and third means adapted to receive the delayed signal and the second train of pulses, said third means being operative to sample the levels of the delayed signal at the times of occurrence of predetermined transitions of the second train of pulses and to produce an output having a first value each time that the delayed signal is at a first level at the time of occurrence of an aforesaid transition in the second train of pulses and to produce an output having a second value each time that the delayed signal is at a second level at the time of occurrence of an aforesaid transition in the second train of pulses.
Claim 3
Dependent Claim 69 words
A data converting apparatus in accordance with claim 1 wherein the first means comprises: a first flip-flop having a data input adapted to receive the double density encoded signal and a trigger input adapted to receive the first train of pulses; and a second flip-flop having a data input adapted to receive the double density encoded signal and a trigger input adapted to receive the second train of pulses.
Claim 4
Dependent Claim 103 words
A data converting apparatus in accordance with claim 2 wherein: the first flip-flop has a first output and a second output; the second flip-flop has a first output and a second output; and the first means further comprises: a first AND gate having a first input coupled to the first output of the first flip-flop, a second input coupled to the second output of the second flip-flop, and an output; and a second AND gate having a first input coupled to the first output of the second flip-flop, a second input coupled to the second output of the first flip-flop, and an output.
Claim 5
Dependent Claim 45 words
A data converting apparatus in accordanCe with claim 3 wherein: the second means includes a NOR gate having a first input coupled to the output of the first AND gate, a second input coupled to the output of the second AND gate, and an output.
Claim 6
Dependent Claim 39 words
A data converting apparatus in accordance with claim 4 wherein the third means comprises: a third flip-flop having a data input adapted to receive the delayed signal and a trigger input adapted to receive the second train of pulses.
Claim 7
Dependent Claim 61 words
A data converting apparatus in accordance with claim 5 wherein: the first and second trains of pulses each include pulses each having a width equal to one-half of a bit period of the double density encoded signal; and the second train of pulses is phase displaced with respect to the first train of pulses by one half of a bit period.

References Cited (Backward Citations)

US3587086A Cited
US3508228A Cited
US3623041A Cited
US3699554A Cited
US3671960A Cited
US3697977A Cited
US3691553A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-08-05 1978-02-04 1978-08-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-08-05 1982-02-04 1982-08-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-08-05 1986-02-04 1986-08-06 $7700.00 Window Closed / Lapsed

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