Patent US3828327A successfully refreshed from Google Patents.
US3828327A
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Simplified storage protection and address translation under system mode control in a data processing system
Assignee: International Business Machines Corp
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Filing: 1973-04-30
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Granted: 1974-08-06
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Expires: 1993-04-30
Abstract
Abstract Improved mode control is provided for a computer system whereby system mode can change for each asynchronously occurring interrupt. Mode control includes the functions of privileged instructions, masked interrupts, storage protection and address translation for expanded storage. Any combination of these functions can be active at any instant. Each interrupt level can select its own type of addressing control and with respect to any cycle of operation within the interrupt routine.
Inventors
- 👤 J Petrie
- 👤 N Berglund
- 👤 J Kerr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:00
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4818; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292; G06F12/14; G06F12/1416; G06F12/145; G06F9/4843; G06F9/4881
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
167 words
In a stored program computer system having addresSable main storage means, central processing means, and input/output means, said central processing means including addressing means for addressing a portion of and all of said main storage means, means for fetching and storing data from and within said main storage means, means for arithmetically and logically processing data, means for initiating communication between said main storage means and said input/output means and control means for sequencing operations, said control means including interrupt levels ordered from low to high priority with only one interrupt level being active at anyone time, said interrupt levels being selected by logic within said central processing unit and within said input/output means, the improvement comprising: a plurality of selectable program mode registers containing bits for controlling the operational mode of said computer system, there being one program mode register for each interrupt level, and program mode register selection means responsive to the selected interrupt level for selecting the program mode register for that interrupt level.
Claim 2
Dependent Claim
167 words
In a stored program computer system having addresSable main storage means, central processing means, and input/output means, said central processing means including addressing means for addressing a portion of and all of said main storage means, means for fetching and storing data from and within said main storage means, means for arithmetically and logically processing data, means for initiating communication between said main storage means and said input/output means and control means for sequencing operations, said control means including interrupt levels ordered from low to high priority with only one interrupt level being active at anyone time, said interrupt levels being selected by logic within said central processing unit and within said input/output means, the improvement comprising: a plurality of selectable program mode registers containing bits for controlling the operational mode of said computer system, there being one program mode register for each interrupt level, and program mode register selection means responsive to the selected interrupt level for selecting the program mode register for that interrupt level.
Claim 3
Dependent Claim
17 words
The stored program computer system of claim 1, wherein said interrupt levels are encoded in binary form.
Claim 4
Dependent Claim
35 words
The stored program computer system of claim 1, wherein each program mode register includes a bit position settable to a binary one or zero for representing the presence or absence of an address translation mode.
Claim 5
Dependent Claim
26 words
The stored program computer system of claim 3, wherein said address translation mode is for address translation during the I cycle time of an instruction cycle.
Claim 6
Dependent Claim
26 words
The stored program computer system of claim 3, wherein said address translation mode is for address translation during a first execution cycle of an instruction cycle.
Claim 7
Dependent Claim
26 words
The stored program computer system of claim 3, wherein said address translation mode is for address translation during a second execution cycle of an instruction cycle.
Claim 8
Dependent Claim
36 words
The stored program computer system of claim 1, wherein each program mode register includes a binary bit position settable to a binary one or zero for representing the presence or absence of a privileged operation mode.
Claim 9
Dependent Claim
49 words
The stored program computer system of claim 1, wherein each program mode register includes a bit position settable to a binary one or zero for representing the presence or absence of an input/output mode where said input/output means requires storage access beyond said portion of said main storage means.
Claim 10
Dependent Claim
76 words
The stored program computer system of claim 8 further comprising input/output address registers having a plurality of bit positions settable by bits from said input/output means for addressing said portion of said main storage means and a high order bit position for expanding the addresses in said input/output address registers beyond said portion of said main storage means; and logic means responsive to said input/output mode for setting said high order bit of said input/output registers.
Claim 11
Dependent Claim
49 words
The stored program computer system of claim 9, further comprising logic means for sensing the bit condition of said high order bit position of an input/output register and setting the input/output mode bit position of the selected program mode register to the bit condition sensed by said logic means.
Claim 12
Dependent Claim
34 words
The stored program computer system of claim 1 wherein each program mode register includes a bit position settable to binary one or zero for representing the presence or absence of a storage protection mode.
Claim 13
Dependent Claim
91 words
The stored program computer of claim 11 further comprising register means for storing sets of fetch and write protection bits for sets of storage areas within said main storage means, said sets of fetch and write protection bits being selected by a portion of the address for addressing said main storage means, and logic means responsive to a selected set of fetch and write protection bits and to said storage protection mode bit being a binary one for generating signals for blocking access to and wRiting into said main storage means.
Claim 14
Dependent Claim
25 words
The stored program computer system of claim 12, wherein said signals generated by said logic means are used to indicate fetch and write violation conditions.
Claim 15
Dependent Claim
35 words
The stored program computer system of claim 1 wherein each program mode register includes a bit position settable to a binary one or zero for representing the presence or absence of a masked interrupt mode.
Claim 16
Dependent Claim
46 words
The stored program computer system of claim 14, further comprising logic means responsive to the presence of a masked interrupt mode for generating a signal to inhibit selection of an interrupt level whereby the operation of the computer system continues in the previously selected interrupt level.
Claim 17
Dependent Claim
142 words
The stored program computer system of claim 3 further comprising a plurality of selectable address translation registers containing bits for forming the high order portion of the address for addressing said main storage means beyond said portion, address translation register selection logic means responsive to high order bits of an address to generate signals for selecting one of said address translation registers, translate logic means responsive to the presence of said address translate mode to pass the high order address bits from the selected address translation register to address said main storage means together with the low order address bits from said addressing means and responsive to the absence of said address translate mode to pass the high order address bits from said addressing means to address said main storage means together with the low order address bits from said addressing means.
Claim 18
Dependent Claim
26 words
The stored program computer system of claim 16 wherein said address translation registers include bit positions for storing sets of fetch and write storage protection bits.
Claim 19
Dependent Claim
30 words
The stored program computer system of claim 1 further comprising means for generating a signal for storing the bits from a selected program mode register in said main storage means.
Claim 20
Dependent Claim
29 words
The stored program computer system of claim 1 further comprising means for generating a signal for setting bits from said main storage means into a selected program mode register.
Claim 21
Dependent Claim
29 words
The stored program computer system of claim 16 further comprising means for generating a signal for setting bits from said main storage means into a selected address translation register.
Claim 22
Dependent Claim
29 words
The stored program computer system of claim 16 further comprising means for generating a signal for storing bits from a selected address translation register in said main storage means.
Claim 23
Dependent Claim
32 words
The stored program computer system of claim 3 further comprising logic for generating a program check signal in the absence of a privileged operation mode in response to a privileged operation command.
References Cited (Backward Citations)
US3292151A
Cited
US3303477A
Cited
US3398405A
Cited
US3395392A
Cited
US3553653A
Cited
US3701977A
Cited
US3614740A
Cited
US3740722A
Cited
US3676852A
Cited
US3742458A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-05 | 1978-02-04 | 1978-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-05 | 1982-02-04 | 1982-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-05 | 1986-02-04 | 1986-08-06 | $7700.00 | Window Closed / Lapsed |