Patent US3828271A successfully refreshed from Google Patents.
US3828271A
Expired / Lapsed
US
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Clock and sector mark generator for rotating storage units
Assignee: Unisys Corp
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Filing: 1973-07-27
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Granted: 1974-08-06
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Expires: 1993-07-27
Abstract
Abstract In a rotating storage unit such as a disk pack drive wherein encoded data is recorded on concentric tracks on the disk, the clock signal that times the data as it is recorded on a track or times the data as it is read from a track, along with sector indications, is accurately synthesized from the occurrence of a once-per-revolution signal (index signal) which is slaved to the rotational speed variations of the disk. This index signal may be recorded on the disk. The index signal synchronizes a voltage controlled oscillator to generate the clock pulses. These clock pulses are divided down by a variable modulo counter to produce sector indicating signals. These sector indicating signals are divided down to a once-per-revolution signal that is compared in time of occurrence to the index signal from the disk. The time difference between these two signals generates a control signal that regulates the voltage controlled oscillator.
Inventors
- 👤 F Schwanauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:09
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; G; G11; G11B; G11B20/00; G11B20/10; G11B20/16
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
114 words
A clock and sector mark signal generator for use with a rotating storage medium, having a means for generating a first once-per-revolution signal synchronized to the velocity variations of said storage medium, comprising: means for generating a plurality of clock signals at a predetermined nominal frequency; first means for dividing the clock signals by a selectable factor to generate sector mark signals; second means for dividing the sector mark signals by a selectable factor to generate a second once-per-revolution signal; and means for comparing the occurrence times of the first and second once-per-revolution signals to produce a control signal for regulating the frequency of the plurality of clock signals from said clock generating means.
Claim 2
Dependent Claim
114 words
A clock and sector mark signal generator for use with a rotating storage medium, having a means for generating a first once-per-revolution signal synchronized to the velocity variations of said storage medium, comprising: means for generating a plurality of clock signals at a predetermined nominal frequency; first means for dividing the clock signals by a selectable factor to generate sector mark signals; second means for dividing the sector mark signals by a selectable factor to generate a second once-per-revolution signal; and means for comparing the occurrence times of the first and second once-per-revolution signals to produce a control signal for regulating the frequency of the plurality of clock signals from said clock generating means.
Claim 3
Dependent Claim
83 words
The clock and sector mark signal generator of claim 1 wherein said first means and said second means comprises variable modulo pulse counters, the first variable modulo counter having its input connected to the output of said clock signal generating means and counting the plurality of clock signals from said clock signal generating means, the second variable modulo counter having its input connected to the output of said first variable modulo counter and counting the output signals from said first variable modulo counter.
Claim 4
Dependent Claim
58 words
The clock and sector mark signal generator of claim 1 wherein said means for comparing the occurrence times of the first and second once-per-revolution signals comprises a D-C binary flip-flop circuit, the first once-per-revolution signal being supplied to the C input of said flip-flop and the second once-per-revolution signal being supplied to the D input of said flip-flop.
Claim 5
Dependent Claim
41 words
The clock and sector mark signal generator of claim 3, further comprising means for producIng a control signal for regulating the frequency of the plurality of clock signals from said clock generating means in response to signals from said binary flip-flop.
Claim 6
Dependent Claim
61 words
The clock and sector mark signal generator of claim 4 wherein said means for producing a control signal comprises an integrating circuit utilizing a dual input level inverting amplifier, the Q output of said D-C flip-flop connected to the noninverting input of said amplifier and the Q output of said D-C flip-flop being connected to the inverting input of said amplifier.
Claim 7
Dependent Claim
48 words
The clock and sector mark signal generator of claim 5 wherein said integrating circuit responds to a speed related signal from said rotating storage medium to select a higher gain for lower speeds of said storage medium and a lower gain for higher speeds of said storage medium.
Claim 8
Dependent Claim
41 words
The clock and sector mark signal generator of claim 1, further comprising means for producing a control signal for regulating the frequency of the plurality of clock signals from said clock generating means in response to signals from said comparing means.
Claim 9
Dependent Claim
41 words
The clock and sector mark signal generator of claim 7 wherein said means for providing a control signal comprises an integrating circuit utilizing a dual input level inverting amplifier, the output signals from said comparing means being supplied to said amplifier.
Claim 10
Dependent Claim
48 words
The clock and sector mark signal generator of claim 8 wherein said integrating circuit responds to a speed related signal from said rotating storage medium to select a higher gain for lower speeds of said storage medium and a lower gain for higher speeds of said storage medium.
Claim 11
Dependent Claim
18 words
The clock and sector mark signal generator of claim 5 wherein said integrating circuit has a selectable gain.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-05 | 1978-02-04 | 1978-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-05 | 1982-02-04 | 1982-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-05 | 1986-02-04 | 1986-08-06 | $7700.00 | Window Closed / Lapsed |