Patent US4232866A successfully refreshed from Google Patents.
Patent US3828137A successfully refreshed from Google Patents.
US3828137A
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Digital communication system
Assignee: National Aeronautics and Space Administration
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Filing: 1972-11-28
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Granted: 1974-08-06
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Expires: 1992-11-28
Abstract
Abstract A digital communication system for parallel operation of 16 or more transceiver units with the use of only four interconnecting wires. A remote synchronization circuit produces unit address control words sequentially in data frames of 16 words. Means are provided in each transceiver unit to decode calling signals and to transmit calling and data signals. The transceivers communicate with each other over one data line. The synchronization unit communicates the address control information to the transceiver units over an address line and further provides the timing information over a clock line. A reference voltage level or ground line completes the interconnecting four wire hookup.
Inventors
- 👤 L Monford
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 05:14
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0685; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
184 words
A digital communication system having four interconnecting conducting lines including a data line, an address line, a clock line, and a reference voltage level or ground line and comprising: a. a plurality of digital data transceiver units connected to said digital data line; b. a central synchronization unit for producing on said address line, address control word digital information referencing each of said plural transceiver units in a predetermined time sequence, and for producing, on said clock line, clock pulse signals for use in timing the operation of digital circuitry in said transceiver units; c. means in each of said transceiver units for serially receiving said address control word information, for decoding said address information, and for recognizing an address code corresponding to another particular transceiver unit and an address code for itself; and d. means responsive to said recognition means for serially transmitting on said data line digital data information from an input device upon recognition of its own address code and for receiving and decoding digital data from said data line upon recognition of the address of said other particular transceiver unit.
Claim 2
Dependent Claim
184 words
A digital communication system having four interconnecting conducting lines including a data line, an address line, a clock line, and a reference voltage level or ground line and comprising: a. a plurality of digital data transceiver units connected to said digital data line; b. a central synchronization unit for producing on said address line, address control word digital information referencing each of said plural transceiver units in a predetermined time sequence, and for producing, on said clock line, clock pulse signals for use in timing the operation of digital circuitry in said transceiver units; c. means in each of said transceiver units for serially receiving said address control word information, for decoding said address information, and for recognizing an address code corresponding to another particular transceiver unit and an address code for itself; and d. means responsive to said recognition means for serially transmitting on said data line digital data information from an input device upon recognition of its own address code and for receiving and decoding digital data from said data line upon recognition of the address of said other particular transceiver unit.
Claim 3
Dependent Claim
56 words
A system as defined in claim 1 further including in each transceiver unit address initialization means for transmitting its own address code information on said data line in the regular time sequence allocated for a second transceiver unit in said predetermined time sequence when it is desired to initiate a call to said second transceiver unit.
Claim 4
Dependent Claim
33 words
A system as defined in claim 2 further including means in each transceiver unit for signaling a calling signal upon receipt of address information on said data line from a second transceiver unit.
Claim 5
Dependent Claim
34 words
A system as defined in claim 1 wherein said data from a digital data input device comprises voice data from a digital voice modulator and said digital communication system comprises a digital telephone system.
Claim 6
Dependent Claim
40 words
A system as defined in claim 1 wherein said address control word digital information comprises binary numerical information words at least four binary digits in length, thereby providing for 16 or more such transceiver units in a four conductor system.
Claim 7
Dependent Claim
157 words
A digital communication system having 16 or more parallel operational data transceiver units interconnected by at least three lines, a clock line, an address line, and a data line and comprising: a single digital data synchronization unit for providing on said address data line, address code digital information referencing said transceiver units and a single clock for producing, on said clock line, timing data for use by said transceiver units; means in said transceiver units for transmitting dIgital data on said digital data line connecting all said transceiver units; means in said transceiver units for generating a calling signal from a first transceiver unit to any or all of the other of said transceiver units; means in said transceiver units for recognizing said calling signal from a particular transceiver unit; and means in said transceiver units responsive to said recognizing means for decoding digital information presented on said data line when a particular transceiver unit is called.
Claim 8
Dependent Claim
157 words
A digital communication system having 16 or more parallel operational data transceiver units interconnected by at least three lines, a clock line, an address line, and a data line and comprising: a single digital data synchronization unit for providing on said address data line, address code digital information referencing said transceiver units and a single clock for producing, on said clock line, timing data for use by said transceiver units; means in said transceiver units for transmitting dIgital data on said digital data line connecting all said transceiver units; means in said transceiver units for generating a calling signal from a first transceiver unit to any or all of the other of said transceiver units; means in said transceiver units for recognizing said calling signal from a particular transceiver unit; and means in said transceiver units responsive to said recognizing means for decoding digital information presented on said data line when a particular transceiver unit is called.
Claim 9
Dependent Claim
19 words
The apparatus of claim 6 and further including means for converting said decoded digital data to analog data form.
Claim 10
Dependent Claim
37 words
The apparatus of claim 6 wherein said digital signals are applied to said address line and said data line in serial digital data form, but are processed internally in said transceiver units in parallel digital data form.
Claim 11
Dependent Claim
52 words
The apparatus of claim 6 wherein said recognizing means comprises a serial-to-parallel register and plural digital comparator means including a caller''s name digital comparator and a fixed name digital comparator each capable of producing output recognition signals on an output line when positive comparison is effected with a programmed digital input signal.
Claim 12
Dependent Claim
29 words
The apparatus of claim 6 wherein all the digital circuitry in said transceiver units are operated synchronously by clock signals from said single clock in said data synchronization unit.
Claim 13
Dependent Claim
54 words
The apparatus of claim 6 wherein said means for generating a calling signal from a transceiver unit comprises a parallel-to-serial shift register and means for supplying said register with a digital code representative of said first or calling transceiver unit, and means for coupling the output of said shift register onto said data line.
Claim 14
Dependent Claim
29 words
The apparatus of claim 6 wherein said digital information decoding means and said recognizing means share in common multifunctional, digital circuitry comprising a single multifunctional, digital serial-to-parallel shift register.
References Cited (Backward Citations)
US3544976A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-05 | 1978-02-04 | 1978-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-05 | 1982-02-04 | 1982-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-05 | 1986-02-04 | 1986-08-06 | $7700.00 | Window Closed / Lapsed |