Gated bilateral switching semiconductor device

Claim 1

A gated bilateral switching semiconductor device comprising in combination: a. a main body of single crystal semiconductor material having first, second and third layers of alternating conductivity types forming first and second p-n junctions between said first and second layers and between said second and third layers, respectively; said first and third layers each having therein a region of a conductivity type opposite that of the main portion of said first and third layers and forming third and fourth p-n junctions, said regions being in non-overlapping relationship to each other; and a second region of conductivity type opposite that of said third layer within said third layer remote from said first region therein providing a fifth p-n junction; b. a first main electrode overlying and secured to said first layer including said first region therein; c. a second main electrode having an opening therein such that said electrode is overlying and secured to said third layer including said first region but not said second region therein; d. a layer of active glass overlying and secured to said second region and spaced from said second main electrode, said active glass layer exhibiting high impedance characteristics when a voltage below a predetermined threshold is applied thereacross and low impedance characteristics when a voltage above said predetermined threshold is applied thereacross; and e. gate electrode means overlying and secured to said active glass layer for applying gating signals to said device; whereby said device exhibits high or low impedance characteristics between said main electrodes in dependence upon a gating signal applied to said gate electrodes producing a voltage across said active glass layer below or above said predetermined threshold voltage.