Switching circuit employing latching type semiconductor devices and associated control transistors

Claim 1

A crosspoint switching array for establishing particular signal transmission paths between selected transmission line groups of first and second sets of transmission line groups, each transmission line group of the first set being associated with each transmission line group of the second set at separate ones of a multiplicity of crosspoints, each transmission line group having at least two signal lines and a control line, said switching array comprising a controlled latching semiconductor device for each signal transmission path between a transmission line group of the first set and a transmission line group of the second set at each crosspoint, each of said semiconductor devices having first and second signal electrodes and a gate electrode, the first and second signal electrodes being adapted to be connected between signal lines in said first and second sets of transmission line groups; a resistance for each controlled latching semiconductor device connected between the gate electrode and the second signal electrode of the associated semiconductor device; transistor means at each crosspoint having an emitter connection for connecting to the control line of the transmission line group of one of the sets of transmission line groups and a base connection for connecting to the control line of the transmission line group of the other of the sets of transmission line groups; each transistor means including a transistor associated with each controlled latching semiconductor device at the crosspoint, each transistor having an emitter, a base, and a collector with its emitter connected only to the emitter connection of the transistor means and to the emitter of each transistor at the same crosspoint and with its base connected only to the base connection of the transistor means and to the base of each transistor at the same crosspoint, the only paths for current flow between the control lines at the crosspoint being across the emitter-base junctions of the transistors at the crosspoint; and a blocking means connected in series between the gate electrode of each controlled latching semiconductor device and the collector of its associated transistor for blocking the flow of current along a path from the signal line connected to the first signal electrode of the semiconductor device, into the semiconductor device, from the gate electrode to the collector, through the transistor, and from the base connection of the transistor means to the control line connected to the base connection; each blocking means being connected only to the juncture of the gate electrode and the resistance and to the collector of the transistor; the application of coincident pulses to selected control lines at said first and second sets of transmission line groups causing current flow through the transistors at the selected crosspoints, thereby causing collector current to flow into the gate electrodes of the associated controlled latching semiconductor devices and establishing particular signal transmission paths between the selected transmission line groups.