Clock synchronization circuit

Claim 2

A clock circuit for a half-duplex, asynchronous data link, comprising: a. transceiver means for transmitting and receiving over said data link pulse trains containing encoded data in the form of the presence or absence of essentially square-wave pulses, each said pulse train beginning with an identifiable start pulse which ends in a falling edge; b. means for producing a steady enabling signal whenever said transciever is not transmitting a start pulse; c. a pair of ring-connected monostable multivibrators connected to trigger each other; d. flip-flop means for enabling one of said monostable multivibrators; e. means for triggering said flip-flop means alternately in response to said steady enabling signal and in response to the falling edge of the start pulse of a pulse train received over said data link; And f. counter means for restoring said flip-flop means at the end of a predetermined number of cycles of said monostable multivibrators.

Claim 3

The circuit of claim 1, further comprising: g. a third monostable multivibrator; h. a second flip-flop means; and i. transition-responsive means for generating a transition-indicating spike whenever a level transition appears in said received pulse train; said third monostable multivibrator, second flip-flop, and transition-responsive means being so interconnected with said pair of monostable multivibrators that application of said spike to said third multivibrator prevents one of said pair of multivibrators from being triggered for a predetermined length of time, and that application of said spike to said second flip-flop causes the other of said pair of multivibrators to be triggered if it is not already triggered.

Claim 6

Apparatus for receiving and transmitting coded pulse trains, comprising: a. transmitter-receiver means; b. shift register means arranged to encode transmitted pulse trains and to decode received pulse trains; c. clock means including a pair of monostable multivibrators connected to trigger one another for timing the operation of said shift register means; d. clock control means for operating said clock means in discrete sequences of n cycles each, n being the number of bits in the pulse train; and e. synchronizing means operative when said apparatus is in the receive mode to synchronize said clock means with level transitions in the received pulse train, said synchronizing means including: i. spike-producing means connected to said transmitter-receiver means to produce a spike whenever a level transition occurs in a received pulse train; ii. retarding monostable multivibrator means connected to be triggered by said spike and to inhibit operation of said clock means when said retarding mono is in its unstable condition; and iii. advance flip-flop means connected to said clock means and said spike-producing means so as to trigger said clock means upon the occurrence of a spike prior to the internal triggering of the clock.

Claim 7

Apparatus for receiving and transmitting coded pulse trains, comprising: a. transmitter-receiver means; b. shift register means arranged to encode transmitted pulse trains and to decode received pulse trains; c. clock means including a pair of monostable multivibrators connected to trigger one another for timing the operation of said shift register means; d. clock control means for operating said clock means in discrete sequences of n cycles each, n being the number of bits in the pulse train; and e. synchronizing means operative when said apparatus is in the receive mode to synchronize said clock means with level transitions in the received pulse train, said synchronizing means including: i. spike-producing means connected to said transmitter-receiver means to produce a spike whenever a level transition occurs in a received pulse train; ii. retarding monostable multivibrator means connected to be triggered by said spike and to inhibit operation of said clock means when said retarding mono is in its unstable condition; and iii. advance flip-flop means connected to said clock means and said spike-producing means so as to trigger said clock means upon the occurrence of a spike prior to the internal triggering of the clock.

Claim 8

Apparatus according to claim 4, in which said retarding mono means inhibit triggering of the second clock mono by the first, and said advance flip-flop means trigger said first clock mono if said second clock mono is in its unstable condition when said spike occurs.

Claim 9

The apparatus of claim 5, further comprising logic gate means connected to said clock monos, said transmitter-receiver means, and said shift register means to provide a triggering signal to said shift register means coincident with the triggering of said first clock mono when said transmitter-receiver is in the receive mode, and coincident with the triggering of said second clock mono when said transmitter-receiver is in the transmit mode.

Claim 10

The apparatus of claim 4, in which said clock control means include a start-stop flip-flop connected to receive a count at each cycle of said clock means and arranged to produce an output spike when full; said start-stop flip-flop being connected to be start-triggered by the trailing edge of the start pulse of a received pulse train in the receive mode of said transmitter-receiver means, and by an enabling signal iN the transmit mode of said transmitter-receiver means, and to be stop-triggered by said counter output spike.

Claim 11

The apparatus of claim 7, further comprising reset means to clear said counter, said reset means including alternatively operable means to produce a resetting pulse upon either the transmission or reception of a start pulse preceding a data pulse train.

Claim 12

The apparatus of claim 8, further comprising received start pulse detection means, and in which said reset means include a plurality of logic gate means connected to the enabling signal source of said transmitter-receiver means, said start pulse detection means, and said start-stop flip-flop to clear said counter whenever said start-stop flip-flop is in the stopped condition while either said enabling signal is absent, or a received start pulse is being detected by said start pulse detection means.