Matrix scanning circuit for testing a multiplicity of circuit paths

Claim 1

Apparatus for testing a plurality of m X n circuit paths for defective open and shorted conditions, said apparatus comprising a matrix scan circuit having m + n inputs and m X n outputs, means for connecting one end of each of said circuit paths to a corresponding one of said matrix scan circuit outputs, an indicator matrix having m X n indicator elements, means for connecting the other end of each of said circuit paths to a corresponding one of said indicator elements, a source of electric potential coupled to each of said indicator elements, scanning means selectively coupled to the inputs of said matrix scan circuit and to the reference of said electric potential source for providing a selected plurality of current paths from said electric potential source through said indicator matrix, said circuit paths and said matrix scan circuit to each input of said matrix scan circuit to thereby selectively actuate a corresponding plurality of said indicator elements, said matrix scan circuit being arranged such that coupling of said scanning means to any n-input of said matrix scan circuit provides a corresponding plurality of m current paths and coupling of said scanning means to any m-input of said matrix scan circuit provides a corresponding plurality of n current paths, and means for sequentially scanning said scanning means among said matrix scan circuit m-inputs and n-inputs to thereby sequentially actuate corresponding pluralities of said indicator elements, a failure of any given indicator to actuate being indicative of a defect in a corresponding circuit path.