Patent US3825680A successfully refreshed from Google Patents.
US3825680A
Expired / Lapsed
US
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Receiver for video signals
Assignee: US Philips Corp
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Filing: 1973-01-23
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Granted: 1974-07-23
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Expires: 1993-01-23
Abstract
Abstract A receiver for video signals which are transmitted, for example, by differential pulse code modulation and in which for the recovery of the analog video signal the demodulator is provided with an integrator whose time constant is many times the line period. The output of this integrator is coupled to a fault corrector provided with a fault detector, which fault corrector upon the command of the fault detector replaces a perturbed image line to be applied to the display arrangement by an unperturbed image line which has already been displayed or is still to be displayed.
Inventors
- 👤 L Verhoeven
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:19
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/06; H04B14/066; A; A47; A47C; A47C7/00; A47C7/62; A47C7/68; A47C7/70; H04N; H04N19/00; H04N19/50; H04N19/85; H04N19/89; H04N19/895
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
280 words
Receiver for the reception of video signals including a plurality of horizontal scanning cycles separated by blanking signals of a given fixed blanking level said video signal being pulse code modulated and having code groups characterizing variations occurring in said video signal at given instants, said receiver comprising a pulse code modulation decoder, means for applying the received video signal to said pulse code modulation decoder, said decoder including integrator means having an integration time considerably longer than a horizontal scanning cycle, and including a decoder output terminal means, said receiver further comprising detection means including an input circuit coupled to said decoder for developing a switching signal when the blanking level of the received video signal is greater than a selected error criterion with respect to said fixed blanking level, switching means having first and second input terminal means and an output terminal means, main channel means coupling said pulse code modulator decoder output means to said first switching input terminal for delaying the output signal of said decoder for a period of time corresponding to an integral number horizontal scanning cycles, correction channel means having an output coupled to said second input terminal means of said switching means and an input coupled to a remaining one of said terminal means to change the output signal of said switching means for a period of time corresponding to an integral number horizontal scaning cycles, said main and correction channel means producing video signals mutually delayed for a period of time corresponding to an integral number horizontal scanning cycles, said switching means being responsive to the switching signal to selectively connect the second input of said switching means to its ouTput.
Claim 2
Dependent Claim
280 words
Receiver for the reception of video signals including a plurality of horizontal scanning cycles separated by blanking signals of a given fixed blanking level said video signal being pulse code modulated and having code groups characterizing variations occurring in said video signal at given instants, said receiver comprising a pulse code modulation decoder, means for applying the received video signal to said pulse code modulation decoder, said decoder including integrator means having an integration time considerably longer than a horizontal scanning cycle, and including a decoder output terminal means, said receiver further comprising detection means including an input circuit coupled to said decoder for developing a switching signal when the blanking level of the received video signal is greater than a selected error criterion with respect to said fixed blanking level, switching means having first and second input terminal means and an output terminal means, main channel means coupling said pulse code modulator decoder output means to said first switching input terminal for delaying the output signal of said decoder for a period of time corresponding to an integral number horizontal scanning cycles, correction channel means having an output coupled to said second input terminal means of said switching means and an input coupled to a remaining one of said terminal means to change the output signal of said switching means for a period of time corresponding to an integral number horizontal scaning cycles, said main and correction channel means producing video signals mutually delayed for a period of time corresponding to an integral number horizontal scanning cycles, said switching means being responsive to the switching signal to selectively connect the second input of said switching means to its ouTput.
Claim 3
Dependent Claim
28 words
A receiver as claimed in claim 1, wherein the main channel comprises a delay line whose delay period is equal to an integral number of horizontal scanning cycles.
Claim 4
Dependent Claim
28 words
A receiver as claimed in claim 2, wherein the correction channel comprises a delay line whose delay period is equal to an integral number of horizontal scanning cycles.
Claim 5
Dependent Claim
44 words
A receiver as claimed in claim 3, wherein the delay period of the delay lines incorporated in the main channel and in the correction channel are mutually equal, while the input of the correction channel is coupled to the output of the main channel.
Claim 6
Dependent Claim
25 words
A receiver as claimed in claim 3, wherein the input of the correction circuit is coupled to the output terminal means of the switching means.
Claim 7
Dependent Claim
90 words
A receiver as claimed in claim 1, adapted for the reception of video signals being differential pulse code modulated, said applying means comprising a series-to-parallel converter means for receiving said code groups, said integrator means comprising a binary adder circuit means coupled to said converter for adding the binary words each determined by a code group, said binary adder circuit comprising a number of parallel output leads, and said detection means comprising a selection gate having a number of inputs coupled to said parallel output leads of the adder circuit.
Claim 8
Independent Claim
110 words
A method for receiving pulse code modulated signals having periodic fixed level portions and code groups representative of said fixed level portions and baseband signal variations, said method comprising decoding said PCM signals by integrating with a time constant longer than the interval between said fixed level portions, detecting when a received code group representative of one of said fixed level portions is greater than a selected error criterion with respect to a stored code group representative of said fixed level portions, and changing the time of providing said baseband signal for a time equal to an integer multiple of said interval upon detecting that said error criterion is exceeded.
Claim 9
Independent Claim
110 words
A method for receiving pulse code modulated signals having periodic fixed level portions and code groups representative of said fixed level portions and baseband signal variations, said method comprising decoding said PCM signals by integrating with a time constant longer than the interval between said fixed level portions, detecting when a received code group representative of one of said fixed level portions is greater than a selected error criterion with respect to a stored code group representative of said fixed level portions, and changing the time of providing said baseband signal for a time equal to an integer multiple of said interval upon detecting that said error criterion is exceeded.
Claim 10
Dependent Claim
26 words
A method as claimed in claim 7 wherein said detecting step comprises detecting when there is any error between said received stored and received code groups.
Claim 11
Dependent Claim
34 words
A method as claimed in claim 7 wherein said PCM signals comprise differential PCM, and further comprising converting series to parallel bits before said decoding step, and said integrating step comprises adding said bits.
Claim 12
Dependent Claim
21 words
A method as claimed in claim 7 wherein said changing step comprises time delaying the time of providing said baseband signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-22 | 1978-01-21 | 1978-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-22 | 1982-01-21 | 1982-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-22 | 1986-01-21 | 1986-07-23 | $7700.00 | Window Closed / Lapsed |